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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

Fixed header info in some testbenches

This commit is contained in:
Konstantin Pavlov 2020-02-25 15:38:02 +03:00
parent c189b88688
commit b8064ecef9
4 changed files with 24 additions and 4 deletions

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@ -1,7 +1,12 @@
//------------------------------------------------------------------------------
// adder_tree_tb.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
// RXI - PIN400M
// INFO ------------------------------------------------------------------------
// testbench for adder_tree.sv module
`timescale 1ns / 1ps
module adder_tree_tb();

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@ -1,7 +1,12 @@
//------------------------------------------------------------------------------
// leave_one_hot_tb.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
// RXI - PIN400M
// INFO ------------------------------------------------------------------------
// testbench for leave_one_hot.sv module
`timescale 1ns / 1ps
module leave_one_hot_tb();

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@ -1,7 +1,12 @@
//------------------------------------------------------------------------------
// pulse_gen_tb.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
// RXI - PIN400M
// INFO ------------------------------------------------------------------------
// testbench for pulse_gen.sv module
`timescale 1ns / 1ps
module pulse_gen_tb();

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@ -1,7 +1,12 @@
//------------------------------------------------------------------------------
// pulse_stretch_tb.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
// RXI - PIN400M
// INFO ------------------------------------------------------------------------
// testbench for pulse_stretch.sv module
`timescale 1ns / 1ps
module pulse_stretch_tb();