From b81fda635dec1dcb40b868227e422dcb95ca457f Mon Sep 17 00:00:00 2001 From: Konstantin Pavlov Date: Mon, 22 May 2023 13:53:54 +0300 Subject: [PATCH] Fixed out[] initialization --- debounce_v1.v | 2 +- debounce_v2.sv | 16 ++++++++-------- debounce_v2.v | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/debounce_v1.v b/debounce_v1.v index 56e7814..a76b8a1 100644 --- a/debounce_v1.v +++ b/debounce_v1.v @@ -45,7 +45,7 @@ module debounce_v1 #( parameter input ena, input [WIDTH-1:0] in, - output reg [WIDTH-1:0] out + output reg [WIDTH-1:0] out = 0 ); diff --git a/debounce_v2.sv b/debounce_v2.sv index af280fa..807f4b5 100644 --- a/debounce_v2.sv +++ b/debounce_v2.sv @@ -47,7 +47,7 @@ module debounce_v2 #( parameter input ena, input [WIDTH-1:0] in, - output logic [WIDTH-1:0] out + output logic [WIDTH-1:0] out = '0 ); @@ -78,15 +78,15 @@ module debounce_v2 #( parameter assign do_sample = s_clk_rise[SAMPLING_FACTOR]; - logic [WIDTH-1:0] in_is_high = 0; - logic [WIDTH-1:0] in_is_low = 0; + logic [WIDTH-1:0] in_is_high = '0; + logic [WIDTH-1:0] in_is_low = '0; always_ff @(posedge clk) begin if (~nrst) begin - out[WIDTH-1:0] <= 0; + out[WIDTH-1:0] <= '0; - in_is_high[WIDTH-1:0] <= 0; - in_is_low[WIDTH-1:0] <= 0; + in_is_high[WIDTH-1:0] <= '0; + in_is_low[WIDTH-1:0] <= '0; end else if (ena && do_sample) begin // making decisions for outputs @@ -105,8 +105,8 @@ module debounce_v2 #( parameter end // for // resetting flags to initialize new sample window - in_is_high[WIDTH-1:0] <= 0; - in_is_low[WIDTH-1:0] <= 0; + in_is_high[WIDTH-1:0] <= '0; + in_is_low[WIDTH-1:0] <= '0; end else begin diff --git a/debounce_v2.v b/debounce_v2.v index e915daa..95b527d 100644 --- a/debounce_v2.v +++ b/debounce_v2.v @@ -47,7 +47,7 @@ module debounce_v2 #( parameter input ena, input [WIDTH-1:0] in, - output reg [WIDTH-1:0] out + output reg [WIDTH-1:0] out = 0 );