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https://github.com/pConst/basic_verilog.git
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Fixed out[] initialization
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71303a0823
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@ -45,7 +45,7 @@ module debounce_v1 #( parameter
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input ena,
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input ena,
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input [WIDTH-1:0] in,
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input [WIDTH-1:0] in,
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output reg [WIDTH-1:0] out
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output reg [WIDTH-1:0] out = 0
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);
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);
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@ -47,7 +47,7 @@ module debounce_v2 #( parameter
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input ena,
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input ena,
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input [WIDTH-1:0] in,
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input [WIDTH-1:0] in,
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output logic [WIDTH-1:0] out
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output logic [WIDTH-1:0] out = '0
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);
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);
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@ -78,15 +78,15 @@ module debounce_v2 #( parameter
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assign do_sample = s_clk_rise[SAMPLING_FACTOR];
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assign do_sample = s_clk_rise[SAMPLING_FACTOR];
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logic [WIDTH-1:0] in_is_high = 0;
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logic [WIDTH-1:0] in_is_high = '0;
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logic [WIDTH-1:0] in_is_low = 0;
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logic [WIDTH-1:0] in_is_low = '0;
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (~nrst) begin
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if (~nrst) begin
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out[WIDTH-1:0] <= 0;
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out[WIDTH-1:0] <= '0;
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in_is_high[WIDTH-1:0] <= 0;
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in_is_high[WIDTH-1:0] <= '0;
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in_is_low[WIDTH-1:0] <= 0;
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in_is_low[WIDTH-1:0] <= '0;
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end else if (ena && do_sample) begin
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end else if (ena && do_sample) begin
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// making decisions for outputs
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// making decisions for outputs
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@ -105,8 +105,8 @@ module debounce_v2 #( parameter
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end // for
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end // for
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// resetting flags to initialize new sample window
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// resetting flags to initialize new sample window
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in_is_high[WIDTH-1:0] <= 0;
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in_is_high[WIDTH-1:0] <= '0;
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in_is_low[WIDTH-1:0] <= 0;
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in_is_low[WIDTH-1:0] <= '0;
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end else begin
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end else begin
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@ -47,7 +47,7 @@ module debounce_v2 #( parameter
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input ena,
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input ena,
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input [WIDTH-1:0] in,
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input [WIDTH-1:0] in,
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output reg [WIDTH-1:0] out
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output reg [WIDTH-1:0] out = 0
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);
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);
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