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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

Fixed out[] initialization

This commit is contained in:
Konstantin Pavlov 2023-05-22 13:53:54 +03:00
parent 71303a0823
commit b81fda635d
3 changed files with 10 additions and 10 deletions

View File

@ -45,7 +45,7 @@ module debounce_v1 #( parameter
input ena,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out
output reg [WIDTH-1:0] out = 0
);

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@ -47,7 +47,7 @@ module debounce_v2 #( parameter
input ena,
input [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
output logic [WIDTH-1:0] out = '0
);
@ -78,15 +78,15 @@ module debounce_v2 #( parameter
assign do_sample = s_clk_rise[SAMPLING_FACTOR];
logic [WIDTH-1:0] in_is_high = 0;
logic [WIDTH-1:0] in_is_low = 0;
logic [WIDTH-1:0] in_is_high = '0;
logic [WIDTH-1:0] in_is_low = '0;
always_ff @(posedge clk) begin
if (~nrst) begin
out[WIDTH-1:0] <= 0;
out[WIDTH-1:0] <= '0;
in_is_high[WIDTH-1:0] <= 0;
in_is_low[WIDTH-1:0] <= 0;
in_is_high[WIDTH-1:0] <= '0;
in_is_low[WIDTH-1:0] <= '0;
end else if (ena && do_sample) begin
// making decisions for outputs
@ -105,8 +105,8 @@ module debounce_v2 #( parameter
end // for
// resetting flags to initialize new sample window
in_is_high[WIDTH-1:0] <= 0;
in_is_low[WIDTH-1:0] <= 0;
in_is_high[WIDTH-1:0] <= '0;
in_is_low[WIDTH-1:0] <= '0;
end else begin

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@ -47,7 +47,7 @@ module debounce_v2 #( parameter
input ena,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out
output reg [WIDTH-1:0] out = 0
);