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Updated Gray functions

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This commit is contained in:
Konstantin Pavlov 2023-02-24 05:59:40 +03:00
parent 0523320552
commit baea1069cb
8 changed files with 231 additions and 363 deletions
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84
ActionBurst.v
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@ -1,84 +0,0 @@
//--------------------------------------------------------------------------------
// ActionBurst.v
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Module is designed to generate one-shot trigger pulses on multiple channels (default is 8)
// Every output channel is triggered only once
// Channels get triggered in sequense from out[0] to out[8]
// That is useful when you need to start some tasks in exact order, but there are no convinient signals to line them up.
// Instance of ActionBurst() is started by high level on start input and the only way to stop generation before all channels get triggered is to reset the instance
/* --- INSTANTIATION TEMPLATE BEGIN ---
ActionBurst AB1 (
.clk( ),
.nrst( 1'b1 ),
.step_wdth( ),
.start( ),
.busy( ),
.out( )
);
defparam AB1.WIDTH = 8;
--- INSTANTIATION TEMPLATE END ---*/
module ActionBurst(clk,nrst,step_wdth,start,busy,out);
parameter WIDTH = 8;
input wire clk;
input wire nrst;
input wire [31:0] step_wdth; // Module buffers step_wdth in PG instance on the SECOND cycle ater start applyed!
input wire start;
output reg busy = 0;
output wire [(WIDTH-1):0] out;
wire PgOut;
reg [31:0] state = 0;
//reg [31:0] step_wdth_buf = 0; // buffering is done in PG
PulseGen PG(
.clk( clk ),
.nrst( start || busy ),
.low_wdth( step_wdth[31:0] ),
.high_wdth( 32'b1 ),
.rpt( 1'b1 ),
.start( busy ),
.busy( ),
.out( PgOut )
);
always @ (posedge clk) begin
if (~nrst) begin
state[31:0] <= 0;
end else begin
if (~busy) begin
if (start) begin // buffering input values
state[31:0] <= 0;
//step_wdth_buf[31:0] <= step_wdth[31:0]; // buffering is done in PG
busy <= 1;
end // start
end else begin
if (PgOut) begin
if (state != (WIDTH-1)) begin
state[31:0] <= state[31:0] + 1'b1;
end else begin
busy <= 0;
end // state
end // PgOut
end // busy
end // nrst
end
genvar i;
generate
for (i=0; i<WIDTH; i=i+1) begin : AB_GEN_FOR
assign out[i] = PgOut && ( i == state[31:0] );
end
endgenerate
endmodule

93
ActionBurst2.v
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//--------------------------------------------------------------------------------
// ActionBurst2.v
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Module is designed to generate one-shot trigger pulses on multiple channels (default is 8)
// Every output channel is triggered only once
// Channels get triggered in sequense from out[0] to out[8]
// That is useful when you need to start some tasks in exact order, but there are no convinient signals to line them up.
// Instance of ActionBurst() is started by high level on start input and the only way to stop generation before all channels get triggered is to reset the instance
// This version of ActionBurst features different step widths
/* --- INSTANTIATION TEMPLATE BEGIN ---
ActionBurst2 AB1 (
.clk( ),
.nrst( 1'b1 ),
.step_wdths( {32'h00000001,32'h00000002,32'h00000003,32'h00000004,32'h00000005,32'h00000006,32'h00000007,32'h00000008} ),
.start( ),
.busy( ),
.out( )
);
defparam AB1.WIDTH = 8;
--- INSTANTIATION TEMPLATE END ---*/
module ActionBurst2(clk,nrst,step_wdths,start,busy,out);
parameter WIDTH = 8;
input wire clk;
input wire nrst;
input wire [(WIDTH*32-1):0] step_wdths;
input wire start;
output reg busy = 0;
output wire [(WIDTH-1):0] out;
wire PgOut;
reg [31:0] state = 0;
wire [31:0] lw;
genvar j;
generate
for(j=0; j<32; j=j+1) begin : LW_FOR
assign lw[j] = step_wdths[state[31:0]*32+j];
end
endgenerate
PulseGen PG(
.clk( clk ),
.nrst( start || busy ),
.low_wdth( lw[31:0] ),
.high_wdth( 32'b1 ),
.rpt( 1'b0 ),
.start( busy ),
.busy( ),
.out( PgOut )
);
always @ (posedge clk) begin
if (~nrst) begin
state[31:0] <= 0;
end else begin
if (~busy) begin
if (start) begin // buffering input values
state[31:0] <= 0;
//step_wdth_buf[31:0] <= step_wdth[31:0]; // buffering is done in PG
busy <= 1;
end // start
end else begin
if (PgOut) begin
if (state != (WIDTH-1)) begin
state[31:0] <= state[31:0] + 1'b1;
end else begin
busy <= 0;
end // state
end // PgOut
end // busy
end // nrst
end
genvar i;
generate
for (i=0; i<WIDTH; i=i+1) begin : AB_GEN_FOR
assign out[i] = PgOut && ( i == state[31:0] );
end
endgenerate
endmodule

88
ActionBurst2_tb.v
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@ -1,88 +0,0 @@
//--------------------------------------------------------------------------------
// ActionBurst2_tb.v
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
//
//
`timescale 1ns / 1ps
module ActionBurst2_tb();
reg clk200;
initial begin
#0 clk200 = 1;
forever
#2.5 clk200 = ~clk200;
end
reg rst;
initial begin
#10.2 rst = 1;
#5 rst = 0;
//#10000;
forever begin
#9985 rst = ~rst;
#5 rst = ~rst;
end
end
wire nrst = ~rst;
reg rst_once;
initial begin // initializing non-X data before PLL starts
#10.2 rst_once = 1;
#5 rst_once = 0;
end
initial begin
#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
#5 rst_once = 0;
end
wire nrst_once = ~rst_once;
wire [31:0] DerivedClocks;
ClkDivider CD1 (
.clk(clk200),
.nrst(nrst_once),
.out(DerivedClocks[31:0]));
defparam CD1.WIDTH = 32;
wire [31:0] E_DerivedClocks;
EdgeDetect ED1 (
.clk(clk200),
.nrst(nrst_once),
.in(DerivedClocks[31:0]),
.rising(E_DerivedClocks[31:0]),
.falling(),
.both()
);
defparam ED1.WIDTH = 32;
wire [15:0] RandomNumber1;
c_rand RNG1 (
.clk(clk200),
.rst(rst_once),
.reseed(1'b0),
.seed_val(DerivedClocks[31:0]),
.out(RandomNumber1[15:0]));
reg start;
initial begin
#100.2 start = 1;
#5 start = 0;
end
wire out;
ActionBurst2 AB1 (
.clk(clk200),
.nrst(nrst),
.step_wdths( {32'h00000001,32'h00000002,32'h00000003,32'h00000004,32'h00000005,32'h00000006,32'h00000007,32'h00000008} ),
.start( start ),
.busy(),
.out(out)
);
defparam AB1.WIDTH = 8;
endmodule

89
ActionBurst_tb.v
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@ -1,89 +0,0 @@
//--------------------------------------------------------------------------------
// ActionBurst_tb.v
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
//
//
`timescale 1ns / 1ps
module ActionBurst_tb();
reg clk200;
initial begin
#0 clk200 = 1;
forever
#2.5 clk200 = ~clk200;
end
reg rst;
initial begin
#10.2 rst = 1;
#5 rst = 0;
//#10000;
forever begin
#9985 rst = ~rst;
#5 rst = ~rst;
end
end
wire nrst = ~rst;
reg rst_once;
initial begin // initializing non-X data before PLL starts
#10.2 rst_once = 1;
#5 rst_once = 0;
end
initial begin
#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
#5 rst_once = 0;
end
wire nrst_once = ~rst_once;
wire [31:0] DerivedClocks;
ClkDivider CD1 (
.clk(clk200),
.nrst(nrst_once),
.out(DerivedClocks[31:0]));
defparam CD1.WIDTH = 32;
wire [31:0] E_DerivedClocks;
EdgeDetect ED1 (
.clk(clk200),
.nrst(nrst_once),
.in(DerivedClocks[31:0]),
.rising(E_DerivedClocks[31:0]),
.falling(),
.both()
);
defparam ED1.WIDTH = 32;
wire [15:0] RandomNumber1;
c_rand RNG1 (
.clk(clk200),
.rst(rst_once),
.reseed(1'b0),
.seed_val(DerivedClocks[31:0]),
.out(RandomNumber1[15:0]));
reg start;
initial begin
#100.2 start = 1;
#5 start = 0;
end
wire out;
ActionBurst AB1 (
.clk(clk200),
.nrst(nrst),
.step_wdth(32'd1),
.start(1'b1),
.busy(),
.out(out)
);
defparam AB1.WIDTH = 32;
endmodule

7
bin2gray.sv
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@ -1,5 +1,6 @@
//------------------------------------------------------------------------------
// bin2gray.sv
// published as part of https://github.com/pConst/basic_verilog
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
@ -26,9 +27,9 @@ module bin2gray #( parameter
output logic[WIDTH-1:0] gray_out
);
always_comb begin
gray_out[WIDTH-1:0] = bin_in[WIDTH-1:0]^(bin_in[WIDTH-1:0]>>1);
end
always_comb begin
gray_out[WIDTH-1:0] = bin_in[WIDTH-1:0] ^ ( bin_in[WIDTH-1:0] >> 1 );
end
endmodule

14
gray2bin.sv
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@ -1,5 +1,6 @@
//------------------------------------------------------------------------------
// gray2bin.sv
// published as part of https://github.com/pConst/basic_verilog
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
@ -23,15 +24,16 @@ module gray2bin #( parameter
WIDTH = 32
)(
input [WIDTH-1:0] gray_in,
output [WIDTH-1:0] bin_out
output logic [WIDTH-1:0] bin_out
);
genvar i;
generate
for( i=0; i<WIDTH; i++ ) begin
assign bin_out[i] = ^gray_in[WIDTH-1:i];
always_comb begin
bin_out[WIDTH-1:0] = '0;
for( integer i=0; i<WIDTH; i++ ) begin
bin_out[WIDTH-1:0] ^= gray_in[WIDTH-1:0] >> i;
end
end
endgenerate
endmodule

44
gray_functions.vh Normal file
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//------------------------------------------------------------------------------
// gray_functions.vh
// published as part of https://github.com/pConst/basic_verilog
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
// INFO ------------------------------------------------------------------------
// Gray code parametrizable converter functions
//
// Parametrized classes are supported by Vivado, NOT supported by Quartus.
// Please use bin2gray.sv and gray2bin.sv conventional modules instead.
//
// Call syntax:
// ============
// assign a[63:0] = gray_functions#(64)::bin2gray( b[63:0] );
// assign c[255:0] = gray_functions#(256)::gray2bin( d[255:0] );
//
virtual class gray_functions #( parameter
WIDTH = 32
);
static function [WIDTH-1:0] bin2gray(
input [WIDTH-1:0] bin
);
bin2gray[WIDTH-1:0] = bin[WIDTH-1:0] ^ ( bin[WIDTH-1:0] >> 1 );
endfunction
static function [WIDTH-1:0] gray2bin(
input [WIDTH-1:0] gray
);
gray2bin[WIDTH-1:0] = '0;
for( integer i=0; i<WIDTH; i++ ) begin
gray2bin[WIDTH-1:0] ^= gray[WIDTH-1:0] >> i;
end
endfunction
endclass

175
gray_functions_tb.sv Normal file
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//------------------------------------------------------------------------------
// gray_functions_tb.sv
// published as part of https://github.com/pConst/basic_verilog
// Konstantin Pavlov, pavlovconst@gmail.com
//------------------------------------------------------------------------------
// INFO ------------------------------------------------------------------------
// Testbench for gray_functions class
// use this define to make some things differently in simulation
`define SIMULATION yes
`timescale 1ns / 1ps
module gray_functions_tb();
initial begin
// Print out time markers in nanoseconds
// Example: $display("[T=%0t] start=%d", $realtime, start);
$timeformat(-9, 3, " ns");
// seed value setting is intentionally manual to achieve repeatability between sim runs
$urandom( 1 ); // SEED value
end
logic clk200;
sim_clk_gen #(
.FREQ( 200_000_000 ), // in Hz
.PHASE( 0 ), // in degrees
.DUTY( 50 ), // in percentage
.DISTORT( 10 ) // in picoseconds
) clk200_gen (
.ena( 1'b1 ),
.clk( clk200 ),
.clkd( )
);
logic nrst_once;
logic [31:0] clk200_div;
clk_divider #(
.WIDTH( 32 )
) cd1 (
.clk( clk200 ),
.nrst( nrst_once ),
.ena( 1'b1 ),
.out( clk200_div[31:0] )
);
logic [31:0] clk200_div_rise;
edge_detect ed1[31:0] (
.clk( {32{clk200}} ),
.anrst( {32{nrst_once}} ),
.in( clk200_div[31:0] ),
.rising( clk200_div_rise[31:0] ),
.falling( ),
.both( )
);
// external device "asynchronous" clock
logic clk33;
logic clk33d;
sim_clk_gen #(
.FREQ( 200_000_000 ), // in Hz
.PHASE( 0 ), // in degrees
.DUTY( 50 ), // in percentage
.DISTORT( 1000 ) // in picoseconds
) clk33_gen (
.ena( 1'b1 ),
.clk( clk33 ),
.clkd( clk33d )
);
logic rst;
initial begin
rst = 1'b0; // initialization
repeat( 1 ) @(posedge clk200);
forever begin
repeat( 1 ) @(posedge clk200); // synchronous rise
rst = 1'b1;
//$urandom( 1 ); // uncomment to get the same random pattern EVERY nrst
repeat( 2 ) @(posedge clk200); // synchronous fall, controls rst pulse width
rst = 1'b0;
repeat( 100 ) @(posedge clk200); // controls test body width
end
end
logic nrst;
assign nrst = ~rst;
logic rst_once;
initial begin
rst_once = 1'b0; // initialization
repeat( 1 ) @(posedge clk200);
repeat( 1 ) @(posedge clk200); // synchronous rise
rst_once = 1'b1;
repeat( 2 ) @(posedge clk200); // synchronous fall, controls rst_once pulse width
rst_once = 1'b0;
end
//logic nrst_once; // declared before
assign nrst_once = ~rst_once;
// random pattern generation
logic [31:0] rnd_data;
always_ff @(posedge clk200) begin
rnd_data[31:0] <= $urandom;
end
initial forever begin
@(posedge nrst);
$display("[T=%0t] rnd_data[]=%h", $realtime, rnd_data[31:0]);
end
// helper start strobe appears unpredictable up to 20 clocks after nrst
logic start;
initial forever begin
start = 1'b0; // initialization
@(posedge nrst); // synchronous rise after EVERY nrst
repeat( $urandom_range(0, 20) ) @(posedge clk200);
start = 1'b1;
@(posedge clk200); // synchronous fall exactly 1 clock after rise
start = 1'b0;
end
initial begin
// #10000 $stop;
// #10000 $finish;
end
// Module under test ===========================================================
logic [15:0] seq_cntr = '0;
logic [31:0] id = '0;
always_ff @(posedge clk200) begin
if( ~nrst_once ) begin
seq_cntr[15:0] <= '0;
id[31:0] <= '0;
end else begin
// incrementing sequence counter
if( seq_cntr[15:0]!= '1 ) begin
seq_cntr[15:0] <= seq_cntr[15:0] + 1'b1;
end
if( seq_cntr[15:0]<300 ) begin
id[31:0] <= '1;
//id[31:0] <= {4{rnd_data[15:0]}};
end else begin
id[31:0] <= '0;
end
end
end
`include "gray_functions.vh"
logic [15:0] gray;
logic [15:0] bin;
always_comb begin
gray[15:0] = gray_functions#(16)::bin2gray( seq_cntr[15:0] );
bin[15:0] = gray_functions#(16)::gray2bin( gray[15:0] );
end
endmodule