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Fix clog usage in pulse_stretch.sv

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Konstantin Pavlov 2023-05-23 11:49:24 +03:00
parent f0edcd3af0
commit bb0897a409
1 changed files with 50 additions and 45 deletions
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95
pulse_stretch.sv
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@ -1,13 +1,15 @@
//--------------------------------------------------------------------------------
// pulse_stretch.sv
// published as part of https://github.com/pConst/basic_verilog
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Pulse stretcher/extender module
// this implementftion uses a simple delay line or counter to stretch pulses
// WIDTH parameter sets output pulse width
// if you need variable output poulse width, see pulse_gen.sv module
//
// - this implementftion uses a simple delay line or counter to stretch pulses
// - WIDTH parameter sets output pulse width
// - if you need variable output poulse width, see pulse_gen.sv module
/* --- INSTANTIATION TEMPLATE BEGIN ---
@ -24,6 +26,7 @@ pulse_stretch #(
--- INSTANTIATION TEMPLATE END ---*/
module pulse_stretch #( parameter
WIDTH = 8,
USE_CNTR = 0 // ==0 - stretcher is implemented on delay line
@ -37,55 +40,57 @@ module pulse_stretch #( parameter
);
localparam CNTR_WIDTH = $clog2(WIDTH) + 1;
localparam CNTR_W = $clog2(WIDTH+1);
generate
generate
//==========================================================================
if( WIDTH == 0 ) begin
assign out = 0;
if ( WIDTH == 0 ) begin
assign out = 0;
end else if( WIDTH == 1 ) begin
assign out = in;
end else begin
if( USE_CNTR == '0 ) begin
// delay line
logic [WIDTH-1:0] shifter = '0;
always_ff @(posedge clk) begin
if( ~nrst ) begin
shifter[WIDTH-1:0] <= '0;
end else begin
// shifting
shifter[WIDTH-1:0] <= {shifter[WIDTH-2:0],in};
end // nrst
end // always
assign out = (shifter[WIDTH-1:0] != '0);
//==========================================================================
end else if( WIDTH == 1 ) begin
assign out = in;
//==========================================================================
end else begin
// counter
if( USE_CNTR == '0 ) begin
// delay line
logic [CNTR_WIDTH-1:0] cntr = '0;
always_ff @(posedge clk) begin
if( ~nrst ) begin
cntr[CNTR_WIDTH-1:0] <= '0;
end else begin
if( in ) begin
// setting counter
cntr[CNTR_WIDTH-1:0] <= CNTR_WIDTH'(WIDTH);
end else if( out ) begin
// decrementing counter
cntr[CNTR_WIDTH-1:0] <= cntr[CNTR_WIDTH-1:0] - 1'b1;
end
end // nrst
end // always
logic [WIDTH-1:0] shifter = '0;
always_ff @(posedge clk) begin
if( ~nrst ) begin
shifter[WIDTH-1:0] <= '0;
end else begin
// shifting
shifter[WIDTH-1:0] <= {shifter[WIDTH-2:0],in};
end // nrst
end // always
assign out = (cntr[CNTR_WIDTH-1:0] != '0);
assign out = (shifter[WIDTH-1:0] != '0);
end
end // if WIDTH
endgenerate
end else begin
// counter
logic [CNTR_W-1:0] cntr = '0;
always_ff @(posedge clk) begin
if( ~nrst ) begin
cntr[CNTR_W-1:0] <= '0;
end else begin
if( in ) begin
// setting counter
cntr[CNTR_W-1:0] <= CNTR_W'(WIDTH);
end else if( out ) begin
// decrementing counter
cntr[CNTR_W-1:0] <= cntr[CNTR_W-1:0] - 1'b1;
end
end // nrst
end // always
assign out = (cntr[CNTR_W-1:0] != '0);
end
end // if WIDTH
endgenerate
endmodule