mirror of
https://github.com/pConst/basic_verilog.git
synced 2025-01-14 06:42:54 +08:00
SImplified reverse_vector.sv code
This commit is contained in:
parent
0e19b10433
commit
bcc548f914
@ -22,32 +22,18 @@ reverse_vector #(
|
|||||||
|
|
||||||
|
|
||||||
module reverse_vector #( parameter
|
module reverse_vector #( parameter
|
||||||
WIDTH = 8 // WIDTH must be >=2
|
WIDTH = 8
|
||||||
)(
|
)(
|
||||||
input [(WIDTH-1):0] in,
|
input [(WIDTH-1):0] in,
|
||||||
output logic [(WIDTH-1):0] out
|
output logic [(WIDTH-1):0] out
|
||||||
);
|
);
|
||||||
|
|
||||||
|
integer i;
|
||||||
genvar i;
|
always_comb begin
|
||||||
|
for (i = 0; i < WIDTH ; i++) begin : gen_reverse
|
||||||
generate
|
out[i] = in[(WIDTH-1)-i];
|
||||||
for (i = 0; i < (WIDTH/2) ; i++) begin : gen1
|
end // for
|
||||||
always_comb begin
|
end // always_comb
|
||||||
out[i] = in[WIDTH-1-i];
|
|
||||||
out[WIDTH-1-i] = in[i];
|
|
||||||
end // always_comb
|
|
||||||
end // for
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
// additional assign needed when WIDTH is odd
|
|
||||||
generate
|
|
||||||
if ( WIDTH%2 ) begin : gen2
|
|
||||||
always_comb begin
|
|
||||||
out[WIDTH/2] = in[WIDTH/2];
|
|
||||||
end // always_comb
|
|
||||||
end // for
|
|
||||||
endgenerate
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
Loading…
x
Reference in New Issue
Block a user