Updated test prj up to Vivado 2021.2

example_projects/vivado_test_prj_template_v3/.gitignore

@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+# .gitignore for Xilinx Vivado
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# INFO ------------------------------------------------------------------------
+# rename the file to ".gitignore" and place into your Vivado project directory
+#
+
+
+*.cache
+*.hw
+*.gen
+*.ip_user_files
+*.runs
+*.sim
+.Xil
+
+*.srcs/sources*/bd/**
+!*.srcs/sources*/bd/**/*.xci
+*.srcs/sources*/ip/**
+!*.srcs/sources*/ip/**/*.xci
+
+.ioplanning
+*.jou
+*.log
+*.str
+*.tmp
+usage_statistics_webtalk.*
+
+*.xsa
+

example_projects/vivado_test_prj_template_v3/clean_vivado.bat

@@ -0,0 +1,49 @@
+@echo off
+rem ------------------------------------------------------------------------------
+rem  clean_vivado.bat
+rem  published as part of https://github.com/pConst/basic_verilog
+rem  Konstantin Pavlov, pavlovconst@gmail.com
+rem ------------------------------------------------------------------------------
+
+rem Use this file as a boilerplate for your custom clean script
+rem for Vivado/Vitis projects
+
+
+for /R %%f in (*.xpr) do (
+  echo "Project name is %%~nf"
+
+  del /s /f /q .\.Xil\*
+  rmdir /s /q  .\.Xil\
+
+  del /s /f /q .\%%~nf.cache\*
+  rmdir /s /q  .\%%~nf.cache\
+
+  del /s /f /q .\%%~nf.gen\*
+  rmdir /s /q  .\%%~nf.gen\
+
+  del /s /f /q .\%%~nf.hw\*
+  rmdir /s /q  .\%%~nf.hw\
+
+  del /s /f /q .\%%~nf.ip_user_files\*
+  rmdir /s /q  .\%%~nf.ip_user_files\
+
+  del /s /f /q .\%%~nf.runs\*
+  rmdir /s /q  .\%%~nf.runs\
+
+  del /s /f /q .\%%~nf.sim\*
+  rmdir /s /q  .\%%~nf.sim\
+
+
+  del /s /f /q .\*.jou
+  del /s /f /q .\*.log
+  del /s /f /q .\*.str
+  del /s /f /q .\*.tmp
+  del /s /f /q .\usage_statistics_webtalk.*
+
+  del /s /f /q *.xsa
+
+)
+
+pause
+goto :eof
+

example_projects/vivado_test_prj_template_v3/src/clk_divider.sv

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+//------------------------------------------------------------------------------
+// clk_divider.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  Divides main clock to get derivative slower synchronous clocks
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+clk_divider #(
+  .WIDTH( 32 )
+) CD1 (
+  .clk( clk ),
+  .nrst( 1'b1 ),
+  .ena( 1'b1 ),
+  .out(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module clk_divider #( parameter
+  WIDTH = 32
+)(
+  input clk,
+  input nrst,
+  input ena,
+  output logic [(WIDTH-1):0] out = 0
+);
+
+
+always_ff @(posedge clk) begin
+  if ( ~nrst ) begin
+    out[(WIDTH-1):0] <= 0;
+  end else if (ena) begin
+    out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
+  end
+end
+
+endmodule

example_projects/vivado_test_prj_template_v3/src/clogb2.svh

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+//------------------------------------------------------------------------------
+// clogb2.svh
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  Calculates counter/address width based on specified vector/RAM depth
+//
+//  Function should be instantiated inside a module
+//  But you are free to call it from anywhere by its hierarchical name
+//
+//  To add clogb2 function to your module:
+//  `include "clogb2.svh"
+//
+
+function integer clogb2;
+  input integer depth;
+
+  for( clogb2=0; depth>0; clogb2=clogb2+1 ) begin
+    depth = depth >> 1;
+  end
+endfunction
+

example_projects/vivado_test_prj_template_v3/src/define.svh

@@ -0,0 +1,32 @@
+//------------------------------------------------------------------------------
+// Vivado test project template
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+
+// Vivado bugfix ===============================================================
+
+  // This is a workaround for Vivado bug of not providing errors
+  //   when using undeclared signals in your code
+  //   See https://forums.xilinx.com/t5/Synthesis/Bug-in-handling-undeclared-signals-in-instance-statement-named/td-p/300127
+    `define VIVADO_MODULE_HEADER `default_nettype none
+    `define VIVADO_MODULE_FOOTER `default_nettype wire
+
+  // Declare these stubs to safely reuse your Vivado modules in non-Xilinx FPGA projects
+    //`define VIVADO_MODULE_HEADER
+    //`define VIVADO_MODULE_FOOTER
+
+// =============================================================================
+
+ `define INC( AVAL ) \
+    ``AVAL <= ``AVAL + 1'b1;
+
+ `define DEC( AVAL ) \
+    ``AVAL <= ``AVAL - 1'b1;
+
+ `define SET( AVAL ) \
+    ``AVAL <= 1'b1;
+
+ `define RESET( AVAL ) \
+    ``AVAL <= 1'b0;

example_projects/vivado_test_prj_template_v3/src/delay.sv

@@ -0,0 +1,211 @@
+//------------------------------------------------------------------------------
+// delay.v
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO -------------------------------------------------------------------------
+// Static Delay for arbitrary signal, v2
+// Another equivalent names for this module:
+//          conveyor.sv
+//          synchronizer.sv
+//
+// Tip for Xilinx-based implementations: Leave nrst=1'b1 and ena=1'b1 on
+// purpose of inferring Xilinx`s SRL16E/SRL32E primitives
+//
+//
+// CAUTION: delay module is widely used for synchronizing signals across clock
+//   domains. When synchronizing, please exclude input data paths from timing
+//   analisys manually by writing appropriate set_false_path SDC constraint
+//
+// Version 2 introduces "ALTERA_BLOCK_RAM" option to implement delays using
+//   block RAM. Quartus can make shifters on block RAM aautomatically
+//   using 'altshift_taps' internal module when "Auto Shift Register
+//   Replacement" option is ON
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+delay #(
+    .LENGTH( 2 ),
+    .WIDTH( 1 ),
+    .TYPE( "CELLS" ),
+    .REGISTER_OUTPUTS( "FALSE" )
+) S1 (
+    .clk( clk ),
+    .nrst( 1'b1 ),
+    .ena( 1'b1 ),
+
+    .in(  ),
+    .out(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module delay #( parameter
+  LENGTH = 2,                  // delay/synchronizer chain length
+  WIDTH = 1,                   // signal width
+
+  TYPE = "CELLS",              // "ALTERA_BLOCK_RAM" infers block ram fifo
+                               //   "ALTERA_TAPS" infers altshift_taps
+                               //   all other values infer registers
+
+  REGISTER_OUTPUTS = "FALSE",  // for block RAM implementations: "TRUE" means that
+                               //   last delay stage will be implemented
+                               //   by means of cell registers to improve timing
+                               //   all other values infer block RAMs only
+
+  CNTR_W = $clog2(LENGTH)
+)(
+  input clk,
+  input nrst,
+  input ena,
+
+  input [WIDTH-1:0] in,
+  output [WIDTH-1:0] out
+);
+
+generate
+
+  if ( LENGTH == 0 ) begin
+
+    assign out[WIDTH-1:0] = in[WIDTH-1:0];
+
+  end else if( LENGTH == 1 ) begin
+
+    logic [WIDTH-1:0] data = '0;
+    always_ff @(posedge clk) begin
+      if( ~nrst ) begin
+        data[WIDTH-1:0] <= '0;
+      end else if( ena ) begin
+        data[WIDTH-1:0] <= in[WIDTH-1:0];
+      end
+    end
+    assign out[WIDTH-1:0] = data[WIDTH-1:0];
+
+  end else begin
+    if( TYPE=="ALTERA_BLOCK_RAM" && LENGTH>=3 ) begin
+
+      logic [WIDTH-1:0] fifo_out;
+      logic full;
+      logic [CNTR_W-1:0] usedw;
+
+      logic fifo_out_ena;
+      if( REGISTER_OUTPUTS=="TRUE" ) begin
+        assign fifo_out_ena = (usedw[CNTR_W-1:0] == LENGTH-1);
+      end else begin
+        assign fifo_out_ena = full;
+      end
+
+      scfifo #(
+        .LPM_WIDTH( WIDTH ),
+        .LPM_NUMWORDS( LENGTH ),   // must be at least 4
+        .LPM_WIDTHU( CNTR_W ),
+        .LPM_SHOWAHEAD( "ON" ),
+        .UNDERFLOW_CHECKING( "ON" ),
+        .OVERFLOW_CHECKING( "ON" ),
+        .ENABLE_ECC( "FALSE" ),
+        .ALLOW_RWCYCLE_WHEN_FULL( "ON" ),
+        .USE_EAB( "ON" )
+      ) internal_fifo (
+        .clock( clk ),
+        .aclr( 1'b0 ),
+        .sclr( ~nrst ),
+
+        .data( in[WIDTH-1:0] ),
+        .wrreq( ena ),
+        .rdreq( ena && fifo_out_ena ),
+
+        .q( fifo_out[WIDTH-1:0] ),
+        .empty(  ),
+        .full( full ),
+        .almost_full(  ),
+        .almost_empty(  ),
+        .usedw( usedw[CNTR_W-1:0] ),
+        .eccstatus(  )
+      );
+
+      logic [WIDTH-1:0] reg_out = '0;
+      always_ff @(posedge clk) begin
+        if( ~nrst ) begin
+          reg_out[WIDTH-1:0] <= '0;
+        end else if( ena && fifo_out_ena ) begin
+          reg_out[WIDTH-1:0] <= fifo_out[WIDTH-1:0];
+        end
+      end
+
+      if( REGISTER_OUTPUTS=="TRUE" ) begin
+        assign out[WIDTH-1:0] = reg_out[WIDTH-1:0];
+      end else begin
+        // avoiding first word fall-through
+        assign out[WIDTH-1:0] = (fifo_out_ena)?(fifo_out[WIDTH-1:0]):('0);
+      end
+
+    end else if( TYPE=="ALTERA_TAPS" && LENGTH>=2 ) begin
+
+      logic [WIDTH-1:0] fifo_out;
+      logic [CNTR_W-1:0] delay_cntr = CNTR_W'(LENGTH-1);
+
+      logic fifo_out_ena;
+      assign fifo_out_ena = (delay_cntr[CNTR_W-1:0] == '0);
+
+      always_ff @(posedge clk) begin
+        if( ~nrst ) begin
+          delay_cntr[CNTR_W-1:0] <= CNTR_W'(LENGTH-1);
+        end else if( ena && ~fifo_out_ena ) begin
+          delay_cntr[CNTR_W-1:0] <= delay_cntr[CNTR_W-1:0] - 1'b1;
+        end
+      end
+
+      altshift_taps #(
+        .intended_device_family( "Cyclone V" ),
+        .lpm_hint( "RAM_BLOCK_TYPE=AUTO" ),
+        .lpm_type( "altshift_taps" ),
+        .number_of_taps( 1 ),
+        .tap_distance( (REGISTER_OUTPUTS=="TRUE")?(LENGTH-1):(LENGTH) ),  // min. of 3
+        .width( WIDTH )
+      ) internal_taps (
+        //.aclr( 1'b0 ),
+        //.sclr( ~nrst ),
+        .clock( clk ),
+        .clken( ena ),
+        .shiftin( in[WIDTH-1:0] ),
+        .shiftout( fifo_out[WIDTH-1:0] )
+      );
+
+      if( REGISTER_OUTPUTS=="TRUE" ) begin
+      logic [WIDTH-1:0] reg_out = '0;
+      always_ff @(posedge clk) begin
+        if( ~nrst ) begin
+          reg_out[WIDTH-1:0] <= '0;
+        end else if( ena && fifo_out_ena ) begin
+          reg_out[WIDTH-1:0] <= fifo_out[WIDTH-1:0];
+        end
+      end
+        assign out[WIDTH-1:0] = reg_out[WIDTH-1:0];
+      end else begin
+        assign out[WIDTH-1:0] = fifo_out[WIDTH-1:0];
+      end
+
+    end else begin
+
+      logic [LENGTH:1][WIDTH-1:0] data = '0;
+      always_ff @(posedge clk) begin
+        integer i;
+        if( ~nrst ) begin
+          data <= '0;
+        end else if( ena ) begin
+          for(i=LENGTH-1; i>0; i--) begin
+            data[i+1][WIDTH-1:0] <= data[i][WIDTH-1:0];
+          end
+          data[1][WIDTH-1:0] <= in[WIDTH-1:0];
+        end
+      end
+      assign out[WIDTH-1:0] = data[LENGTH][WIDTH-1:0];
+
+    end // if TYPE
+  end // if LENGTH
+
+endgenerate
+
+endmodule

example_projects/vivado_test_prj_template_v3/src/edge_detect.sv

@@ -0,0 +1,100 @@
+//------------------------------------------------------------------------------
+// edge_detect.sv
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+// Edge detector, ver.4
+//
+// (new!) Added WIDTH parameter to simplify instantiating arrays of edge detectors
+// (new!) Made reset to be asynchronous
+//
+// Added parameter to select combinational implementation (zero clocks delay)
+//                        or registered implementation (one clocks delay)
+//
+// In case when "in" port has toggle rate 100% (changes every clock period)
+//    "rising" and "falling" outputs will completely replicate input
+//    "both" output will be always active in this case
+//
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+edge_detect #(
+  .WIDTH( 32 ),
+  .REGISTER_OUTPUTS( 1'b1 )
+) in_ed (
+  .clk( clk ),
+  .anrst( 1'b1 ),
+  .in( in[31:0] ),
+  .rising( in_rise[31:0] ),
+  .falling(  ),
+  .both(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module edge_detect #( parameter
+  bit [7:0] WIDTH = 1,                 // signal width
+  bit [0:0] REGISTER_OUTPUTS = 1'b0    // 0 - comb. implementation (default)
+                                       // 1 - registered implementation
+)(
+  input clk,
+  input anrst,
+
+  input [WIDTH-1:0] in,
+  output logic [WIDTH-1:0] rising,
+  output logic [WIDTH-1:0] falling,
+  output logic [WIDTH-1:0] both
+);
+
+// data delay line
+logic [WIDTH-1:0] in_d = '0;
+always_ff @(posedge clk or negedge anrst) begin
+  if ( ~anrst ) begin
+    in_d[WIDTH-1:0] <= '0;
+  end else begin
+    in_d[WIDTH-1:0] <= in[WIDTH-1:0];
+  end
+end
+
+logic [WIDTH-1:0] rising_comb;
+logic [WIDTH-1:0] falling_comb;
+logic [WIDTH-1:0] both_comb;
+always_comb begin
+  rising_comb[WIDTH-1:0] = {WIDTH{anrst}} & (in[WIDTH-1:0] & ~in_d[WIDTH-1:0]);
+  falling_comb[WIDTH-1:0] = {WIDTH{anrst}} & (~in[WIDTH-1:0] & in_d[WIDTH-1:0]);
+  both_comb[WIDTH-1:0] = {WIDTH{anrst}} & (rising_comb[WIDTH-1:0] | falling_comb[WIDTH-1:0]);
+end
+
+generate
+  if( REGISTER_OUTPUTS==1'b0 ) begin
+
+    // combinational outputs, no delay
+    always_comb begin
+      rising[WIDTH-1:0] = rising_comb[WIDTH-1:0];
+      falling[WIDTH-1:0] = falling_comb[WIDTH-1:0];
+      both[WIDTH-1:0] = both_comb[WIDTH-1:0];
+    end // always
+
+  end else begin
+
+    // registered outputs, 1 cycle delay
+    always_ff @(posedge clk or negedge anrst) begin
+      if( ~anrst ) begin
+        rising[WIDTH-1:0] <= '0;
+        falling[WIDTH-1:0] <= '0;
+        both[WIDTH-1:0] <= '0;
+      end else begin
+        rising[WIDTH-1:0] <= rising_comb[WIDTH-1:0];
+        falling[WIDTH-1:0] <= falling_comb[WIDTH-1:0];
+        both[WIDTH-1:0] <= both_comb[WIDTH-1:0];
+      end // always
+    end // if
+
+  end // end else
+endgenerate
+
+endmodule

example_projects/vivado_test_prj_template_v3/src/main.sv

@@ -0,0 +1,231 @@
+//------------------------------------------------------------------------------
+// Vivado test project template
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+// Vivado test project template, v3
+// Compatible with Digilent Arty-7020 board
+//
+// - use this as a boilerplate project for fast prototyping
+// - inputs and outputs are registered to allow valid timequest output
+//   even if your custom logic/IPs have combinational outputs
+// - SDC constraint file assigns clk to 500MHz to force fitter to synthesize
+//   the fastest possible circuit
+//
+
+`timescale 1ns / 1ps
+
+`include "define.svh"
+
+
+`define WIDTH 32
+
+module main(
+
+  input clk,         // 125 MHz
+  input [1:0] sw,
+
+  // RGB LEDs
+  output led4_r,led4_g,led4_b,
+  output led5_r,led5_g,led5_b,
+
+  output [3:0] led,
+  input [4:0] btn,
+
+  // PMOD Headers
+  output [4:1] ja_p, [4:1] ja_n,
+  output [4:1] jb_p, [4:1] jb_n,
+
+  // Audio Out
+  output aud_pwm, aud_sd,
+
+  // crypto SDA
+  output crypto_sda,
+
+  // HDMI RX Signals
+  //output hdmi_rx_cec,
+  //output hdmi_rx_clk_p,
+  //output hdmi_rx_clk_n,
+  //output [2:0] hdmi_rx_d_p,
+  //output [2:0] hdmi_rx_d_n,
+  //output hdmi_rx_hpd,
+  //output hdmi_rx_scl,
+  //output hdmi_rx_sda,
+
+  // HDMI TX Signals
+  // output hdmi_tx_cec,
+  // output hdmi_tx_clk_p,
+  // output hdmi_tx_clk_n,
+  // input [2:0] hdmi_tx_d_p,
+  // input [2:0] hdmi_tx_d_n,
+  // output hdmi_tx_hpdn,        // hpdn!
+  // output hdmi_tx_scl,
+  // output hdmi_tx_sda,
+
+  // Single Ended Analog Inputs
+  input [5:0] ck_an_p,
+  input [5:0] ck_an_n,
+
+  // Digital I/O On Outer Analog Header
+  output [5:0] ck_a,
+  // Digital I/O On Inner Analog Header
+  //
+
+  // Digital I/O Low
+  output [13:0] ck_io_low,
+
+  // Digital I/O High
+  output [41:26] ck_io_high,
+
+  // SPI
+  output ck_miso, ck_mosi, ck_sck, ck_ss,
+  // I2C
+  output ck_scl, ck_sda,
+  // Misc
+  output ck_ioa
+);
+
+`VIVADO_MODULE_HEADER
+
+
+// clocks ======================================================================
+
+logic sys_pll_locked;  // asyn
+logic clk125;
+logic clk500;
+
+logic nrst;
+
+clk_wiz_0 sys_pll (
+  .clk_in1( clk ),
+  .resetn(1'b1),
+  .clk_out1( clk125 ),
+  .clk_out2( clk500 ),
+  .locked( sys_pll_locked )
+);
+
+logic [31:0] div_clk125;
+clk_divider #(
+  .WIDTH( 32 )
+) cd_125 (
+  .clk( clk125 ),
+  .nrst( nrst ),
+  .ena( 1'b1 ),
+  .out( div_clk125[31:0] )
+);
+
+logic [31:0] div_clk500;
+clk_divider #(
+  .WIDTH( 32 )
+) cd_500 (
+  .clk( clk500 ),
+  .nrst( nrst ),
+  .ena( 1'b1 ),
+  .out( div_clk500[31:0] )
+);
+
+assign led4_g = div_clk125[25];
+
+// nrst ========================================================================
+logic [1:0] sw_s;
+logic [4:0] btn_s;
+
+always_ff @(posedge clk125) begin
+  nrst <= ~btn_s[0];  // external reset
+end
+
+assign led4_b = ~nrst;
+
+// buttons =====================================================================
+
+delay #(
+    .LENGTH( 2 ),
+    .WIDTH( 6 )
+) sw_SYNC_ATTR (
+    .clk( clk125 ),
+    .nrst( 1'b1 ),
+    .ena( 1'b1 ),
+    .in( {btn[3:0], sw[1:0]} ),
+    .out( {btn_s[3:0], sw_s[1:0]} )
+);
+
+logic [1:0] sw_s_rise;
+logic [4:0] btn_s_rise;
+
+edge_detect #(
+  .WIDTH( 6 )
+) sw_s_ed (
+  .clk( clk125 ),
+  .anrst( nrst ),
+  .in( {btn_s[3:0], sw_s[1:0]} ),
+  .rising( {btn_s_rise[3:0], sw_s_rise[1:0]} ),
+  .falling(  ),
+  .both(  )
+);
+
+// =============================================================================
+
+logic [`WIDTH-1:0] in_data;
+// input registers
+logic [`WIDTH-1:0] in_data_reg = 0;
+always_ff @(posedge clk500) begin
+  if( ~nrst ) begin
+    in_data_reg[`WIDTH-1:0] <= '0;
+  end else begin
+    in_data_reg[`WIDTH-1:0] <= in_data[`WIDTH-1:0];
+  end
+end
+
+// place your test logic here ==================================================
+
+logic [`WIDTH-1:0] out_data_comb = 0;
+always_comb begin
+  out_data_comb[`WIDTH-1:0] <= in_data_reg[`WIDTH-1:0] ^ div_clk500[31:0];
+end
+
+// output registers
+logic [`WIDTH-1:0] out_data = '0;
+always_ff @(posedge clk500) begin
+  if( ~nrst ) begin
+    out_data[`WIDTH-1:0] <= '0;
+  end else begin
+    out_data[`WIDTH-1:0] <= out_data_comb[`WIDTH-1:0];
+  end
+end
+
+
+vio_0 debug_vio (
+  .clk( clk500 ),
+  .probe_out0( in_data[`WIDTH-1:0] ),
+  .probe_in0( div_clk500[31:0] ),
+  .probe_in1( out_data[`WIDTH-1:0] )
+);
+
+// =============================================================================
+
+OBUFDS #(
+  .IOSTANDARD("DEFAULT"),
+  .SLEW("FAST")
+) ja_b [4:1] (
+  .I( div_clk125[24:21] ),
+  .O( ja_p[4:1] ),
+  .OB( ja_n[4:1] )
+);
+
+OBUFDS #(
+  .IOSTANDARD("DEFAULT"),
+  .SLEW("FAST")
+) jb_b [4:1] (
+  .I( div_clk125[24:21] ),
+  .O( jb_p[4:1] ),
+  .OB( jb_n[4:1] )
+);
+
+`include "clogb2.svh"
+
+`VIVADO_MODULE_FOOTER
+
+endmodule
+

example_projects/vivado_test_prj_template_v3/src/physical.xdc

@@ -0,0 +1,178 @@
+#------------------------------------------------------------------------------
+# Vivado test project template
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+
+## Clock signal
+set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk }]
+
+## Switches
+set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]
+set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]
+
+## RGB LEDs
+set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS33 } [get_ports { led4_b }]
+set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { led4_g }]
+set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { led4_r }]
+set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { led5_b }]
+set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { led5_g }]
+set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { led5_r }]
+
+## LEDs
+set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { led[0] }]
+set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { led[1] }]
+set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { led[2] }]
+set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]
+
+## Buttons
+set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]
+set_property -dict { PACKAGE_PIN D20 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]
+set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]
+set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]
+
+## Pmod Header JA
+set_property -dict { PACKAGE_PIN Y18 IOSTANDARD TMDS_33 } [get_ports { ja_p[1] }]
+set_property -dict { PACKAGE_PIN Y19 IOSTANDARD TMDS_33 } [get_ports { ja_n[1] }]
+set_property -dict { PACKAGE_PIN Y16 IOSTANDARD TMDS_33 } [get_ports { ja_p[2] }]
+set_property -dict { PACKAGE_PIN Y17 IOSTANDARD TMDS_33 } [get_ports { ja_n[2] }]
+set_property -dict { PACKAGE_PIN U18 IOSTANDARD TMDS_33 } [get_ports { ja_p[3] }]
+set_property -dict { PACKAGE_PIN U19 IOSTANDARD TMDS_33 } [get_ports { ja_n[3] }]
+set_property -dict { PACKAGE_PIN W18 IOSTANDARD TMDS_33 } [get_ports { ja_p[4] }]
+set_property -dict { PACKAGE_PIN W19 IOSTANDARD TMDS_33 } [get_ports { ja_n[4] }]
+
+## Pmod Header JB
+set_property -dict { PACKAGE_PIN Y14 IOSTANDARD TMDS_33 } [get_ports { jb_n[1] }]
+set_property -dict { PACKAGE_PIN W14 IOSTANDARD TMDS_33 } [get_ports { jb_p[1] }]
+set_property -dict { PACKAGE_PIN T10 IOSTANDARD TMDS_33 } [get_ports { jb_n[2] }]
+set_property -dict { PACKAGE_PIN T11 IOSTANDARD TMDS_33 } [get_ports { jb_p[2] }]
+set_property -dict { PACKAGE_PIN W16 IOSTANDARD TMDS_33 } [get_ports { jb_n[3] }]
+set_property -dict { PACKAGE_PIN V16 IOSTANDARD TMDS_33 } [get_ports { jb_p[3] }]
+set_property -dict { PACKAGE_PIN W13 IOSTANDARD TMDS_33 } [get_ports { jb_n[4] }]
+set_property -dict { PACKAGE_PIN V12 IOSTANDARD TMDS_33 } [get_ports { jb_p[4] }]
+
+## Audio Out
+set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { aud_pwm }]
+set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { aud_sd }]
+
+## Crypto SDA
+set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]
+
+##HDMI RX Signals
+#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]
+#set_property -dict { PACKAGE_PIN N18 IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_p }]
+#set_property -dict { PACKAGE_PIN P19 IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_clk_n }]
+#set_property -dict { PACKAGE_PIN V20 IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_p[0] }]
+#set_property -dict { PACKAGE_PIN W20 IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_n[0] }]
+#set_property -dict { PACKAGE_PIN T20 IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_p[1] }]
+#set_property -dict { PACKAGE_PIN U20 IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_n[1] }]
+#set_property -dict { PACKAGE_PIN N20 IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_p[2] }]
+#set_property -dict { PACKAGE_PIN P20 IOSTANDARD TMDS_33  } [get_ports { hdmi_rx_d_n[2] }]
+#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_hpd }]
+#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]
+#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]
+
+##HDMI TX Signals
+#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]
+#set_property -dict { PACKAGE_PIN L16 IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_p }]
+#set_property -dict { PACKAGE_PIN L17 IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_clk_n }]
+#set_property -dict { PACKAGE_PIN K17 IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_p[0] }]
+#set_property -dict { PACKAGE_PIN K18 IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_n[0] }]
+#set_property -dict { PACKAGE_PIN K19 IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_p[1] }]
+#set_property -dict { PACKAGE_PIN J19 IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_n[1] }]
+#set_property -dict { PACKAGE_PIN J18 IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_p[2] }]
+#set_property -dict { PACKAGE_PIN H18 IOSTANDARD TMDS_33  } [get_ports { hdmi_tx_d_n[2] }]
+#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_hpdn }]
+#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_scl }]
+#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_sda }]
+
+## ChipKit Single Ended Analog Inputs
+## NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5).
+##      These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins CK_A[0-5].
+set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]
+set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]
+set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[1] }]
+set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[1] }]
+set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[2] }]
+set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[2] }]
+set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[3] }]
+set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[3] }]
+set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[4] }]
+set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[4] }]
+set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[5] }]
+set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[5] }]
+
+## ChipKit Digital I/O On Outer Analog Header
+## NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O (Chipkit digital pins 0-5)
+set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS33 } [get_ports { ck_a[0] }]
+set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS33 } [get_ports { ck_a[1] }]
+set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS33 } [get_ports { ck_a[2] }]
+set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { ck_a[3] }]
+set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { ck_a[4] }]
+set_property -dict { PACKAGE_PIN U10 IOSTANDARD LVCMOS33 } [get_ports { ck_a[5] }]
+
+## ChipKit Digital I/O On Inner Analog Header
+## NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11)
+#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS33 } [get_ports { ad_n[0] }]
+#set_property -dict { PACKAGE_PIN C20 IOSTANDARD LVCMOS33 } [get_ports { ad_p[0] }]
+#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { ad_n[12] }]
+#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { ad_p[12] }]
+#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS33 } [get_ports { ad_n[8] }]
+#set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS33 } [get_ports { ad_p[8] }]
+
+## ChipKit Digital I/O Low
+set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[0] }]
+set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[1] }]
+set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[2] }]
+set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[3] }]
+set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[4] }]
+set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[5] }]
+set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[6] }]
+set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[7] }]
+set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[8] }]
+set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[9] }]
+set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[10] }]
+set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[11] }]
+set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[12] }]
+set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io_low[13] }]
+
+## ChipKit Digital I/O High
+set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[26] }]
+set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[27] }]
+set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[28] }]
+set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[29] }]
+set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[30] }]
+set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[31] }]
+set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[32] }]
+set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[33] }]
+set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[34] }]
+set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[35] }]
+set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[36] }]
+set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[37] }]
+set_property -dict { PACKAGE_PIN W8 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[38] }]
+set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[39] }]
+set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[40] }]
+set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 } [get_ports { ck_io_high[41] }]
+
+## ChipKit SPI
+set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]
+set_property -dict { PACKAGE_PIN T12 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]
+set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]
+set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]
+
+## ChipKit I2C
+set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]
+set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]
+
+## Misc. ChipKit signals
+set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]
+
+## Not Connected Pins
+#set_property PACKAGE_PIN F17 [get_ports {netic20_f17}]
+#set_property PACKAGE_PIN G18 [get_ports {netic20_g18}]
+#set_property PACKAGE_PIN T9 [get_ports {netic20_t9}]
+#set_property PACKAGE_PIN U9 [get_ports {netic20_u9}]
+
+
+set_property IOB TRUE [get_ports {*}]

example_projects/vivado_test_prj_template_v3/src/timing.xdc

@@ -0,0 +1,45 @@
+#------------------------------------------------------------------------------
+# Vivado test project template
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+
+# clocks =======================================================================
+create_clock -name clk -period 8.000 -waveform {0.000 4.000} [get_ports { clk }]
+
+
+# ==============================================================================
+#set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]
+#set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+#set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
+#set_property CONFIG_VOLTAGE 3.3 [current_design]
+#set_property CFGBVS VCCO [current_design]
+#set_property CONFIG_MODE SPIx4 [current_design]
+#set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
+#set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+#set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
+#set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
+#set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
+#set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
+
+
+# cross clock false paths ======================================================
+
+#set_false_path -from [get_clocks clk_out1_clk_wiz_0] -to [get_clocks clk_out2_clk_wiz_0]
+#set_false_path -from [get_clocks clk_out2_clk_wiz_0] -to [get_clocks clk_out1_clk_wiz_0]
+
+
+# false paths ==================================================================
+
+# all delay.sv instances with "_SYNC_ATTR" suffix name will be considered not
+#   a delay, but as a synchronizers
+#   see https://www.xilinx.com/support/answers/62136.html for syntax explanation
+set_false_path -to [get_cells -hier -filter {NAME =~ *_SYNC_ATTR/data_reg[1]*}]
+set_false_path -to [get_cells -hier -filter {NAME =~ *_SYNC_ATTR[*]/data_reg[1]*}]
+
+
+# ==============================================================================
+# Other automatically adde dby Vivado ==========================================
+# ==============================================================================
+

example_projects/vivado_test_prj_template_v3/test.xpr

@@ -0,0 +1,322 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2021.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="56" Path="D:/tmp/vivado_test_prj_template_v2/test.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="551196a343084fe495b8bdfd057029bd"/>
+    <Option Name="Part" Val="xc7z020clg400-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2021.2"/>
+    <Option Name="SimulatorVersionModelSim" Val="2020.4"/>
+    <Option Name="SimulatorVersionQuesta" Val="2020.4"/>
+    <Option Name="SimulatorVersionXcelium" Val="20.09.006"/>
+    <Option Name="SimulatorVersionVCS" Val="R-2020.12"/>
+    <Option Name="SimulatorVersionRiviera" Val="2020.10"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="12.0"/>
+    <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="5.3.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="5.3.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="6.3"/>
+    <Option Name="SimulatorGccVersionVCS" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="6.2.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="6.2.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSANumComputeUnits" Val="16"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="6"/>
+    <Option Name="WTModelSimExportSim" Val="6"/>
+    <Option Name="WTQuestaExportSim" Val="6"/>
+    <Option Name="WTIesExportSim" Val="6"/>
+    <Option Name="WTVcsExportSim" Val="6"/>
+    <Option Name="WTRivieraExportSim" Val="6"/>
+    <Option Name="WTActivehdlExportSim" Val="6"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/src/clk_divider.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/src/delay.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
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+        <Option Name="TopModule" Val="main"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
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+        <Option Name="ConstrsType" Val="XDC"/>
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+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="main"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
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+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
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+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
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+    <FileSet Name="vio_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_0" RelGenDir="$PGENDIR/vio_0">
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+        <Option Name="TopModule" Val="vio_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
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+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
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+        <Option Name="TopModule" Val="clk_wiz_0"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
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+      <Option Name="CompiledLib" Val="0"/>
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+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
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+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2021"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design" EnableStepBool="1"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
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+      <ReportStrategy Name="No Reports" Flow="Vivado Implementation 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
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+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
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+        <Step Id="phys_opt_design"/>
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+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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