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Added Quartus Makefile. Customizable and gives faster compilation
This commit is contained in:
Konstantin Pavlov
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f3075c28a2
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207
scripts/Makefile
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207
scripts/Makefile
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#------------------------------------------------------------------------------
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# Makefile for Intel / Altera Quartus
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# Konstantin Pavlov, pavlovconst@gmail.com
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#
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#
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# INFO ------------------------------------------------------------------------
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#
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# - Use this Makefile in linux terminal or on Windows under Cygwin
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#
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# - Default target ("make" command without any options) is intended to get fast
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# compilation and timing analysis. Suitable for general project development
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# and debugging
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#
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# - "make -j" runs timing analysis and *.sof file assembling in parallel. That
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# saves you ~20 seconds every time :)
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#
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# - Specific targets (for example, "make sof") provide you requested results
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# assuming that timing analysis is unnexessary
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#
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# - Check that Quartus and Modelsim directories are in your $PATH. Something like
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# echo $PATH | tr : \\n | grep quartus
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# export PATH = '/cygdrive/c/intelFPGA/17.0/quartus/bin64:$PATH'
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# export PATH = '/cygdrive/c/intelFPGA/17.0/quartus/bin:$PATH'
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# echo $PATH | tr : \\n | grep modelsim
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# export PATH = '/cygdrive/c/intelFPGA/17.0/modelsim_ase/win32aloem:$PATH'
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PROJ_DIR = $(shell pwd)
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PROJ = $(shell ls -1 *.qpf | tail -n1 | awk '{ gsub(".qpf","") } 1' )
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#SRCS = $(shell ls -R1 SOURCE/*.{v,sv,vh,sdc,tcl,hex,bin} 2>/dev/null | grep -v ':' )
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№SRCS = $(shell ls -R1 SOURCE/* )
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QPF = $(PROJ).qpf
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QSF = $(PROJ).qsf
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SOF = ./OUTPUT/$(PROJ).sof
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POF = ./OUTPUT/$(PROJ).pof
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RBF = ./OUTPUT/$(PROJ).rbf
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JAM = ./OUTPUT/$(PROJ).jam
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PRE_SCRIPT = './DEBUG/pre_flow.tcl'
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POST_SCRIPT = './DEBUG/post_flow.tcl'
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MAP_REPORT = ./OUTPUT/$(PROJ).map.rpt
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FIT_REPORT = ./OUTPUT/$(PROJ).fit.rpt
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DSE_CONFIG = $(PROJ).dse
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TARGET_IP = '192.168.1.1'
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TARGET_PORT = 'USB-1'
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TARGET_CHIP = '1'
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.PHONY: all info clean stp gui
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all: sta sof
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info:
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echo -e \\n ' Project directory: ' $(PROJ_DIR) \
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\\n ' Project name: ' $(PROJ) \
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\\n ' Preject sources: ' $(SRCS)
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gui:
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quartus $(QPF) 1>/dev/null
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$(MAP_REPORT): $(SRCS) $(QPF) $(QSF)
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$(shell if test -f $(PRE_SCRIPT); then quartus_sh -t $(PRE_SCRIPT) compile $(PROJ) $(PROJ); fi )
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quartus_map --no_banner \
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--read_settings_files=on \
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--write_settings_files=off \
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--64bit $(PROJ) -c $(PROJ)
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# dont use --effort=fast because it can dramatically increase fitting time
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map: $(PROJ).map.rpt
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$(FIT_REPORT): $(MAP_REPORT)
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# quartus_cdb --read_settings_files=on \
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# --write_settings_files=off \
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# --64bit $(PROJ) -c $(PROJ)
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quartus_fit --no_banner \
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--read_settings_files=on \
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--write_settings_files=off \
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--inner_num=1 \
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--one_fit_attempt=on \
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--pack_register=off \
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--effort=fast \
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--64bit $(PROJ) -c $(PROJ)
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# using --io_smart_recompile for secondary fitter launches is tricky
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fit: $(FIT_REPORT)
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$(SOF): $(FIT_REPORT)
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quartus_asm --no_banner \
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--read_settings_files=off \
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--write_settings_files=off \
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--64bit $(PROJ) -c $(PROJ)
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asm: $(SOF)
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sta: $(FIT_REPORT)
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quartus_sta $(PROJ) -c $(PROJ)
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#$(shell if test -f $(POST_SCRIPT); then quartus_sh -t $(POST_SCRIPT) compile $(PROJ) $(PROJ); fi )
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stap: $(FIT_REPORT)
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quartus_sta --parallel --model=slow $(PROJ) -c $(PROJ)
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#$(shell if test -f $(POST_SCRIPT); then quartus_sh -t $(POST_SCRIPT) compile $(PROJ) $(PROJ); fi )
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$(POF): $(SOF)
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quartus_cpf --no_banner \
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-c $(SOF) $(POF)
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$(RBF): $(SOF)
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quartus_cpf --no_banner \
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-c $(SOF) $(RBF)
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$(JAM): $(SOF)
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quartus_cpf --no_banner \
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-c $(SOF) $(JAM)
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sof: $(SOF)
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pof: $(POF)
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rbf: $(RBF)
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jam: $(JAM)
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prog: sof
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quartus_pgm --no_banner \
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-c "USB-Blaster on $(TARGET_IP) [$(TARGET_PORT)]" -m jtag \
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-o "P;$(SOF)@$(TARGET_CHIP)"
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prog_pof: pof
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quartus_pgm --no_banner \
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-c "USB-Blaster on $(TARGET_IP) [$(TARGET_PORT)]" -m jtag \
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-o "BVP;$(POF)@$(TARGET_CHIP)"
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prog_rbf: rbf
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quartus_pgm --no_banner \
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-c "USB-Blaster on $(TARGET_IP) [$(TARGET_PORT)]" -m jtag \
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-o "BVP;$(RBF)@$(TARGET_CHIP)"
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clean:
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# clean common junk files
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rm -rfv $(PROJ).qws c5_pin_model_dump.txt $(PROJ).ipregen.rpt .qsys_edit/
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# clean compilation databases
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rm -rfv db/ incremental_db/ greybox_tmp/
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# clean output directory
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rm -rfv OUTPUT/
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# clean hard memory controller
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rm -rfv ddr3_hmc_ddr3_0_p0_0_summary.csv ddr3_hmc_ddr3_0_p0_1_summary.csv
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# clean design space explorer files
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rm -rfv dse/ dse1_base.qpf dse1_base.qsf $(PROJ).dse.rpt $(PROJ).archive.rpt
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# clean early power estimator files
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rm -rfv $(PROJ)_early_pwr.csv
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# TODO: add project-specific files to remove here
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dse: $(DSE_CONFIG)
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quartus_dse --no_banner \
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--terminate off \
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--num-parallel-processors 10 \
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--auto-discover-files on \
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--revision $(PROJ) $(PROJ).qpf \
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--use-dse-file $(DSE_CONFIG)
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sim: $(SRCS)
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modelsim -do compile.tcl
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sim_clean:
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gtkwave: $(SRCS)
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# creating VVP file
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iverilog -Wall -g2012 -o iverilog_sim.vvp -s $(SRCS)
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# creating VCD file
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vvp -v iverilog_sim.vvp
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# creating settings file for gtkwave on-the-fly
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echo fontname_waves Verdana 9 > .\gtkwaverc
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echo fontname_signals Verdana 9 >> .\gtkwaverc
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echo fontname_logfile Verdana 9 >> .\gtkwaverc
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echo splash_disable 1 >> .\gtkwaverc
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echo use_roundcaps 1 >> .\gtkwaverc
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echo force_toolbars 1 >> .\gtkwaverc
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echo left_justify_sigs 1 >> .\gtkwaverc
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# launching gtkwave
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# press CTRL+S to save vawe config. gtkwave will open it automatically next time
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gtkwave -r .\gtkwaverc iverilog_sim.vcd wave.gtkw
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# // place this code into your testbench and add signals you want to dump
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# // and navigate during simulation
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# initial begin
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# $dumpfile("iverilog_sim.vcd");
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# $dumpvars( 0, M );
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# #10000 $finish;
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# end
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stp:
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quartus_stp --no_banner \
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$(QPF)
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