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Fixed RS triggers declaration syntax

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This commit is contained in:
Konstantin Pavlov (fm) 2019-01-09 15:12:55 +03:00
parent ba53bc5486
commit cb280f51cf
2 changed files with 12 additions and 12 deletions
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12
reset_set.sv
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@ -23,12 +23,12 @@ reset_set RS1 (
module reset_set(
input wire clk,
input wire nrst,
input wire s,
input wire r,
output reg q = 0, // aka "present state"
output wire nq
input clk,
input nrst,
input s,
input r,
output logic q = 0, // aka "present state"
output nq
);
always_ff @(posedge clk) begin

12
set_reset.sv
View File

@ -23,12 +23,12 @@ set_reset SR1 (
module set_reset(
input wire clk,
input wire nrst,
input wire s,
input wire r,
output reg q = 0, // aka "present state"
output wire nq
input clk,
input nrst,
input s,
input r,
output logic q = 0, // aka "present state"
output nq
);
always_ff @(posedge clk) begin