From cb280f51cf64cc54e9fd6d6d7dc4b42de943d220 Mon Sep 17 00:00:00 2001
From: "Konstantin Pavlov (fm)" <pavlovconst@gmail.com>
Date: Wed, 9 Jan 2019 15:12:55 +0300
Subject: [PATCH] Fixed RS triggers declaration syntax

---
 reset_set.sv | 12 ++++++------
 set_reset.sv | 12 ++++++------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/reset_set.sv b/reset_set.sv
index 43eb022..2da07a8 100644
--- a/reset_set.sv
+++ b/reset_set.sv
@@ -23,12 +23,12 @@ reset_set RS1 (
 
 
 module reset_set(
-  input wire clk,
-  input wire nrst,
-  input wire s,
-  input wire r,
-  output reg q = 0,   // aka "present state"
-  output wire nq
+  input clk,
+  input nrst,
+  input s,
+  input r,
+  output logic q = 0,   // aka "present state"
+  output nq
 );
 
 always_ff @(posedge clk) begin
diff --git a/set_reset.sv b/set_reset.sv
index 2de6c07..db19305 100644
--- a/set_reset.sv
+++ b/set_reset.sv
@@ -23,12 +23,12 @@ set_reset SR1 (
 
 
 module set_reset(
-  input wire clk,
-  input wire nrst,
-  input wire s,
-  input wire r,
-  output reg q = 0,   // aka "present state"
-  output wire nq
+  input clk,
+  input nrst,
+  input s,
+  input r,
+  output logic q = 0,   // aka "present state"
+  output nq
 );
 
 always_ff @(posedge clk) begin