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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

Moved all bencmarks to the separate directory

This commit is contained in:
Konstantin Pavlov 2021-01-26 15:16:11 +03:00
parent 1b844726dc
commit cf3b4f5d20
30 changed files with 30 additions and 18 deletions

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Compilation time results for reference benchmark projects
=========================================================
Xeon E5-2630 v4, RAM 32GB, Windows 7
------------------------------------
quartus_benchmark - 4m 58s ( Quartus Lite 17 )
vivado_benchmark - 5m 58s ( Vivado 2019.2 )
gowin_benchmark - 4m 15s ( Gowin_V1.9.6Beta )
ise_benchmark - 9m 10s ( ISE 12.4 )
Xeon E5-2630 v4, RAM 32GB, Windows 7,
project files on RamDisk
-------------------------------------
quartus_benchmark - 4m 57s ( Quartus Lite 17 )
vivado_benchmark - 5m 56s ( Vivado 2019.2 )
Xeon E5-2630 v4, RAM 32GB, Windows 7,
project files on RamDisk,
HyperThreading OFF
-------------------------------------
quartus_benchmark - 4m 50s ( Quartus Lite 17 )
vivado_benchmark - 5m 43s ( Vivado 2019.2 )

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Compilation time results for reference benchmark projects
=========================================================
Xeon E5-2630 v4, RAM 32GB, Windows 7
------------------------------------
quartus_benchmark - 4m 58s ( Quartus Lite 17 )
vivado_benchmark - 5m 58s ( Vivado 2019.2 )
gowin_benchmark - 4m 15s ( Gowin_V1.9.6Beta )
ise_benchmark - 9m 10s ( ISE 12.4 )
Xeon E5-2630 v4, RAM 32GB, Windows 7, project files on RamDisk
--------------------------------------------------------------
quartus_benchmark - 4m 57s
vivado_benchmark - 5m 56s