Added Vitis HLS scripts and example

example_projects/vitis_hls_test_prj_template_v1/hls_operator.cpp

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+//------------------------------------------------------------------------------
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+#include "hls_operator.h"
+
+int hls_operator( int a, int b ) {
+
+  #pragma HLS DATAFLOW
+
+  static int delta = 1;
+
+  int result = a + b + delta;
+  delta++;
+
+  return result;
+}
+

example_projects/vitis_hls_test_prj_template_v1/hls_operator.h

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+//------------------------------------------------------------------------------
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+#include "ap_int.h"
+
+int hls_operator(int a, int b);
+

example_projects/vitis_hls_test_prj_template_v1/hls_operator_tb.cpp

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+//------------------------------------------------------------------------------
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+#include "ap_int.h"
+
+#include "hls_operator.h"
+
+using namespace std;
+
+int main() {
+
+  const int Ni = 3;
+  const int Nj = 5;
+
+  for (int i = 0; i < Ni; ++i) {
+    for (int j = 1; j < Nj; j=j*2) {
+
+      int result;
+      result = hls_operator( i, j );
+      cout << i << " @ " << j << " = " << result << endl;
+    }
+  }
+
+  return 0;
+}
+

example_projects/vitis_hls_test_prj_template_v1/run_hls.tcl

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+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Create a project
+open_project proj -reset
+add_files hls_operator.cpp
+add_files -tb hls_operator_tb.cpp
+set_top hls_operator
+
+# Create a solution
+open_solution -reset sol1 -flow_target vitis
+set_part {xcvu9p-flga2104-2-i}
+create_clock -period 5 -name default
+
+#csim_design
+csynth_design
+#cosim_design
+#export_design -rtl verilog -format ip_catalog -output /home/kp/tmp
+
+#export_design -flow syn -rtl verilog -format ip_catalog
+#export_design -flow impl -rtl verilog -format ip_catalog
+
+exit
+

example_projects/vitis_hls_test_prj_template_v1/vitis_hls_clean.sh

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+#! /usr/bin/env bash
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to clean Vitis HLS project
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+rm -rf proj
+
+rm vitis_hls.log
+

example_projects/vitis_hls_test_prj_template_v1/vitis_hls_cosim.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to perform HLS component co-simulation
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -eval 'cosim_design'
+

example_projects/vitis_hls_test_prj_template_v1/vitis_hls_csim.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to perform HLS component simulation
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -eval 'csim_design'
+

example_projects/vitis_hls_test_prj_template_v1/vitis_hls_csynth.sh

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+#! /usr/bin/env bash
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to initialize HLS project solution and make CSYNTH compilation step
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+vitis_hls -f run_hls.tcl
+

example_projects/vitis_hls_test_prj_template_v1/vitis_hls_export.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to export HLS component to Vivado IP catalog
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -eval 'export_design -rtl verilog -format ip_catalog'
+

example_projects/vitis_hls_test_prj_template_v1/vitis_hls_impl.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to perform HLS IP synthesis and implementation
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -eval 'export_design -flow impl -rtl verilog -format ip_catalog'
+

example_projects/vitis_hls_test_prj_template_v1/vitis_hls_open_gui.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to open Vitis HLS GUI
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -p proj
+

example_projects/vitis_hls_test_prj_template_v1/vitis_hls_syn.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to perform HLS IP synthesis
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -eval 'export_design -flow syn -rtl verilog -format ip_catalog'
+

scripts_for_xilinx_hls/run_hls.tcl

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+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Create a project
+open_project proj -reset
+add_files hls_operator.cpp
+add_files -tb hls_operator_tb.cpp
+set_top hls_operator
+
+# Create a solution
+open_solution -reset sol1 -flow_target vitis
+set_part {xcvu9p-flga2104-2-i}
+create_clock -period 5 -name default
+
+#csim_design
+csynth_design
+#cosim_design
+#export_design -rtl verilog -format ip_catalog -output /home/kp/tmp
+
+#export_design -flow syn -rtl verilog -format ip_catalog
+#export_design -flow impl -rtl verilog -format ip_catalog
+
+exit
+

scripts_for_xilinx_hls/vitis_hls_clean.sh

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+#! /usr/bin/env bash
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to clean Vitis HLS project
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+rm -rf proj
+
+rm vitis_hls.log
+

scripts_for_xilinx_hls/vitis_hls_cosim.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to perform HLS component co-simulation
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -eval 'cosim_design'
+

scripts_for_xilinx_hls/vitis_hls_csim.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to perform HLS component simulation
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -eval 'csim_design'
+

scripts_for_xilinx_hls/vitis_hls_csynth.sh

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+#! /usr/bin/env bash
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to initialize HLS project solution and make CSYNTH compilation step
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+vitis_hls -f run_hls.tcl
+

scripts_for_xilinx_hls/vitis_hls_export.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to export HLS component to Vivado IP catalog
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -eval 'export_design -rtl verilog -format ip_catalog'
+

scripts_for_xilinx_hls/vitis_hls_impl.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to perform HLS IP synthesis and implementation
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -eval 'export_design -flow impl -rtl verilog -format ip_catalog'
+

scripts_for_xilinx_hls/vitis_hls_open_gui.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to open Vitis HLS GUI
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -p proj
+

scripts_for_xilinx_hls/vitis_hls_syn.sh

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+#! /usr/bin/env bash
+
+#------------------------------------------------------------------------------
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# Script to perform HLS IP synthesis
+# see ../example_projects/vitis_hls_prj_template_v1/ for complete example
+
+if [ ! -d "./proj" ]; then
+  source vitis_hls_csynth.sh
+fi
+
+vitis_hls -eval 'export_design -flow syn -rtl verilog -format ip_catalog'
+