1
0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00

Added paramater to instantiation template of delay.sv

This commit is contained in:
Konstantin Pavlov (fm) 2019-01-09 14:23:45 +03:00
parent 807cc4303d
commit d39ccb2dd7

View File

@ -9,12 +9,15 @@
// conveyor.sv
// synchronizer.sv
//
// Tip for Xilinx-based implementations:
// Leave nrst=1'b1 on purpose of inferring Xilinx`s SRL16E/SRL32E primitives
// Tip for Xilinx-based implementations: Leave nrst=1'b1 and ena=1'b1 on
// purpose of inferring Xilinx`s SRL16E/SRL32E primitives
/* --- INSTANTIATION TEMPLATE BEGIN ---
delay S1 (
delay #(
.N( 2 )
) S1 (
.clk( clk ),
.nrst( 1'b1 ),
.ena( 1'b1 )