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Updated pulse_gen to ver.2
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Konstantin Pavlov
parent
eba4111ce1
commit
d5030cfb5d
197
pulse_gen.sv
197
pulse_gen.sv
@ -1,33 +1,56 @@
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//--------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// pulse_gen.sv
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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// INFO --------------------------------------------------------------------------------
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// Pulse generator module
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// generates one or many pulses of given wigth
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// low_wdth[] and high_wdth[] must NOT be 0
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// INFO ------------------------------------------------------------------------
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// Pulse generator module, ver.2
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//
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// - generates one or many pulses of given width and period
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// - generates constant HIGH, constant LOW, or impulse output
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// - features buffered inputs, so inputs can change continiously during pulse period
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// - generates LOW when idle
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//
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// - Pulse period is (cntr_max[]+1) cycles
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// - If you need to generate constant LOW pulses, then CNTR_WIDTH should allow
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// setting cntr_low[]>cntr_max[]
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//
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// Example 1:
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// let CNTR_WIDTH = 8
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// let cntr_max[7:0] = 2^CNTR_WIDTH-2 = 254, pulse period is 255 cycles
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// cntr_low[7:0]==255 then output will be constant LOW
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// 0<cntr_low[7:0]<=cntr_max[7:0] then output will be generating pulse(s)
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// cntr_low[7:0]==0 then output will be constant HIGH
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//
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// Example 2:
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// let CNTR_WIDTH = 9
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// let cntr_max[8:0] = 255, pulse period is 256 cycles
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// cntr_low[8:0]>255 then output will be constant LOW
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// 0<cntr_low[8:0]<=cntr_max[8:0] then output will be generating pulse(s)
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// cntr_low[8:0]==0 then output will be constant HIGH
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//
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// In Example 2 constant LOW state can be acheived also by disabling start
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// condition or holding reset input, so cntr_low[8:0] and cntr_max[8:0]
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// can be left 8-bit-wide actually
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// CAUTION:
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// - low_wdth[], high_wdth[] and rpt inputs are NOT buffered, so could be changed
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// interactively while pulse_gen is already performing
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// This could be beneficial for implementing PWM-like genetators with
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// variating parameters
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/* --- INSTANTIATION TEMPLATE BEGIN ---
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pulse_gen #(
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.CNTR_WIDTH( 32 )
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.CNTR_WIDTH( 8 )
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) pg1 (
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.clk( clk ),
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.nrst( nrst ),
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.low_width( 2 ),
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.high_width( 2 ),
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.rpt( 1'b0 ),
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.start( 1'b1 ),
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.busy( ),
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.out( )
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.cntr_max( 255 ),
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.cntr_low( 2 ),
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.pulse_out( ),
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.start_strobe,
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.busy( )
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);
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--- INSTANTIATION TEMPLATE END ---*/
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@ -35,95 +58,79 @@ pulse_gen #(
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module pulse_gen #( parameter
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CNTR_WIDTH = 32
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)(
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input clk, // system clock
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input nrst, // negative reset
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input clk,
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input nrst,
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input start, // enables new period start
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input [CNTR_WIDTH-1:0] cntr_max, // counter initilization value, should be > 0
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input [CNTR_WIDTH-1:0] cntr_low, // transition to LOW counter value
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input [CNTR_WIDTH-1:0] low_width,
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input [CNTR_WIDTH-1:0] high_width,
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input rpt,
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output logic pulse_out, // active HIGH output
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input start, // only first front matters
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output busy,
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output logic out = 1'b0
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// status outputs
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output logic start_strobe = 1'b0,
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output busy
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);
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logic [CNTR_WIDTH-1:0] cnt_low = '0;
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logic [CNTR_WIDTH-1:0] cnt_high = '0;
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enum logic [1:0] {IDLE,LOW,HIGH} gen_state;
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logic [CNTR_WIDTH-1:0] seq_cntr = '0;
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logic seq_cntr_0;
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assign seq_cntr_0 = (seq_cntr[CNTR_WIDTH-1:0] == '0);
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// delayed one cycle
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logic seq_cntr_0_d1;
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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out = 1'b0;
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gen_state[1:0] <= IDLE;
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cnt_low[CNTR_WIDTH-1:0] <= '0;
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cnt_high[CNTR_WIDTH-1:0] <= '0;
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if( ~nrst) begin
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seq_cntr_0_d1 <= 0;
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end else begin
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case( gen_state[1:0] )
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IDLE: begin
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if( start ) begin
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out <= 1'b0;
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// latching first pulse widths here
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if( low_width[CNTR_WIDTH-1:0] != '0) begin
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cnt_low[CNTR_WIDTH-1:0] <= low_width[CNTR_WIDTH-1:0] - 1'b1;
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end else begin
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cnt_low[CNTR_WIDTH-1:0] <= '0;
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end
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if( high_width[CNTR_WIDTH-1:0] != '0) begin
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cnt_high[CNTR_WIDTH-1:0] <= high_width[CNTR_WIDTH-1:0] - 1'b1;
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end else begin
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cnt_high[31:0] <= '0;
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end
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gen_state[1:0] <= LOW;
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end
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end // IDLE
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LOW: begin
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if( cnt_low[CNTR_WIDTH-1:0] != 0 ) begin
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out <= 1'b0;
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cnt_low[CNTR_WIDTH-1:0] <= cnt_low[CNTR_WIDTH-1:0] - 1'b1;
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end else begin
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out <= 1'b1;
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gen_state[1:0] <= HIGH;
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end
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end // LOW
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HIGH: begin
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if( cnt_high[CNTR_WIDTH-1:0] != 0 ) begin
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out <= 1'b1;
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cnt_high[CNTR_WIDTH-1:0] <= cnt_high[CNTR_WIDTH-1:0] - 1'b1;
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end else begin
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out <= 1'b0;
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if( rpt ) begin
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// latching repetitive pulse widths here
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if( low_width[CNTR_WIDTH-1:0] != '0) begin
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cnt_low[CNTR_WIDTH-1:0] <= low_width[CNTR_WIDTH-1:0] - 1'b1;
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end else begin
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cnt_low[CNTR_WIDTH-1:0] <= '0;
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end
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if( high_width[CNTR_WIDTH-1:0] != '0) begin
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cnt_high[CNTR_WIDTH-1:0] <= high_width[CNTR_WIDTH-1:0] - 1'b1;
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end else begin
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cnt_high[CNTR_WIDTH-1:0] <= '0;
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end
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gen_state[1:0] <= LOW;
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end else begin
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gen_state[1:0] <= IDLE;
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end
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end
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end // HIGH
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default: gen_state[1:0] <= IDLE;
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endcase // gen_state
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end // nrst
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seq_cntr_0_d1 <= seq_cntr_0;
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end
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end
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assign busy = (gen_state[1:0] != IDLE);
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// first seq_cntr_0 cycle time belongs to pulse period
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// second and further seq_cntr_0 cycles are idle
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assign busy = ~(seq_cntr_0 && seq_cntr_0_d1);
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// buffering cntr_low untill pulse period is over to allow continiously
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// changing inputs
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logic [CNTR_WIDTH-1:0] cntr_low_buf = '0;
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always_ff @(posedge clk) begin
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if( ~nrst ) begin
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seq_cntr[CNTR_WIDTH-1:0] <= '0;
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cntr_low_buf[CNTR_WIDTH-1:0] <= '0;
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start_strobe <= 1'b0;
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end else begin
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if( seq_cntr_0 ) begin
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// don`t start if cntr_max[] is illegal value
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if( start && (cntr_max[CNTR_WIDTH-1:0]!='0) ) begin
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seq_cntr[CNTR_WIDTH-1:0] <= cntr_max[CNTR_WIDTH-1:0];
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cntr_low_buf[CNTR_WIDTH-1:0] <= cntr_low[CNTR_WIDTH-1:0];
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start_strobe <= 1'b1;
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end else begin
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start_strobe <= 1'b0;
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end
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end else begin
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seq_cntr[CNTR_WIDTH-1:0] <= seq_cntr[CNTR_WIDTH-1:0] - 1'b1;
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start_strobe <= 1'b0;
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end
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end // ~nrst
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end
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always_comb begin
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if( ~nrst ) begin
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pulse_out <= 1'b0;
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end else begin
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// busy condition guarantees LOW output when idle
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if( busy &&
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(seq_cntr[CNTR_WIDTH-1:0] >= cntr_low_buf[CNTR_WIDTH-1:0]) ) begin
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pulse_out <= 1'b1;
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end else begin
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pulse_out <= 1'b0;
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end
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end // ~nrst
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end
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endmodule
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@ -18,6 +18,14 @@ initial begin
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#2.5 clk200 = ~clk200;
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end
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// external device "asynchronous" clock
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logic clk33;
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initial begin
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#0 clk33 = 1'b0;
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forever
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#15.151 clk33 = ~clk33;
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end
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logic rst;
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initial begin
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#0 rst = 1'b0;
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@ -63,89 +71,100 @@ edge_detect ed1[31:0] (
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.both( )
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);
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logic [15:0] RandomNumber1;
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logic [31:0] RandomNumber1;
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c_rand rng1 (
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.clk( clk200 ),
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.rst( rst_once ),
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.reseed( 1'b0 ),
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.seed_val( DerivedClocks[31:0] ),
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.rst( 1'b0 ),
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.reseed( rst_once ),
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.seed_val( DerivedClocks[31:0] ^ (DerivedClocks[31:0] << 1) ),
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.out( RandomNumber1[15:0] )
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);
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c_rand rng2 (
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.clk( clk200 ),
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.rst( 1'b0 ),
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.reseed( rst_once ),
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.seed_val( DerivedClocks[31:0] ^ (DerivedClocks[31:0] << 2) ),
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.out( RandomNumber1[31:16] )
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);
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logic start;
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initial begin
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#0 start = 1'b0;
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#100 start = 1'b1;
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#10 start = 1'b0;
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#20 start = 1'b0;
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end
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// Modules under test ==========================================================
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// simple static test
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pulse_gen #(
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.CNTR_WIDTH( 32 )
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/*pulse_gen #(
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.CNTR_WIDTH( 8 )
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) pg1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.low_width( 32'd1 ),
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.high_width( 32'd1 ),
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.rpt( 1'b0 ),
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.start( start ),
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.busy( ),
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.out( )
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.cntr_max( 15 ),
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.cntr_low( 0 ),
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.out( ),
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.busy( )
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);
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*/
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// random test
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pulse_gen #(
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.CNTR_WIDTH( 32 )
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) pg2 (
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.CNTR_WIDTH( 8 )
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) pg1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.low_width( {28'd0,RandomNumber1[3:0]} ),
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.high_width( {28'd0,RandomNumber1[7:4]} ),
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.rpt( 1'b1 ),
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.start( start ),
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.busy( ),
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.out( )
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.start( 1'b1 ),
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.cntr_max( 16 ),
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.cntr_low( {4'b0,RandomNumber1[3:0]} ),
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.out( ),
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.busy( )
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);
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logic [31:0] pg3_in_high_width = '0;
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logic pg3_out;
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logic pg3_out_rise;
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logic [31:0] in_high_width = '0;
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logic out;
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logic out_rise;
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edge_detect pg3_out_ed (
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edge_detect out_ed (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.in( pg3_out ),
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.rising( pg3_out_rise ),
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.in( out ),
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.rising( out_rise ),
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.falling( ),
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.both( )
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);
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always_ff @(posedge clk200) begin
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if( ~nrst_once ) begin
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pg3_in_high_width[31:0] <= 1'b1;
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in_high_width[31:0] <= 1'b0;
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end else begin
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if( pg3_out_rise ) begin
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pg3_in_high_width[31:0] <= pg3_in_high_width[31:0] + 1'b1;
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if( out_rise ) begin
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in_high_width[31:0] <= in_high_width[31:0] + 1'b1;
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end
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end
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end
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// PWM test
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pulse_gen #(
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.CNTR_WIDTH( 32 )
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) pg3 (
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/*pulse_gen #(
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.CNTR_WIDTH( 8 )
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) pg1 (
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.clk( clk200 ),
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.nrst( nrst_once ),
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.low_width( 32'd1 ),
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.high_width( pg3_in_high_width[31:0] ),
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.rpt( 1'b1 ),
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.start( start ),
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.busy( ),
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.out( pg3_out )
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);
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.start( 1'b1 ),
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.cntr_max( 15 ),
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.cntr_low( {4'b0,in_high_width[3:0]} ),
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.out( out ),
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.busy( )
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);*/
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endmodule
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