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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00

Added Vivado-specific scripts

This commit is contained in:
Konstantin Pavlov 2021-06-03 17:01:55 +03:00
parent 48e9ddef7e
commit d8beb37f01
2 changed files with 34 additions and 0 deletions

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scripts/allow_wors.tcl Normal file
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#------------------------------------------------------------------------------
# allow_wors.tcl
# Konstantin Pavlov, pavlovconst@gmail.com
#------------------------------------------------------------------------------
# INFO ------------------------------------------------------------------------
# Simple script to add wor type support in Vivado
# Add this script as a tcl.pre for the Synthesis step
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter compatibilityMode true"

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#------------------------------------------------------------------------------
# jtag_to_axi_master.tcl
# Konstantin Pavlov, pavlovconst@gmail.com
#------------------------------------------------------------------------------
# INFO ------------------------------------------------------------------------
# Use this script to read/write AXI bus through "JTAG to AXI Master" IP-core
# value should be 8 HEX digits == 32bit
proc wr {address value} {
#set address [string range $address 2 [expr {[string length $address]-1}]]
create_hw_axi_txn -force wr_tx [get_hw_axis hw_axi_1] \
-address $address -data $value -len 1 -type write
run_hw_axi -quiet wr_tx
}
proc rd {address} {
#set address [string range $address 2 [expr {[string length $address]-1}]]
create_hw_axi_txn -force rd_tx [get_hw_axis hw_axi_1] \
-address $address -len 1 -type read
run_hw_axi -quiet rd_tx
return 0x[get_property DATA [get_hw_axi_txn rd_tx]]
}