From d971d108cf654a4101cc599c25962e646756266f Mon Sep 17 00:00:00 2001
From: "Konstantin Pavlov (fm)" <pavlovconst@gmail.com>
Date: Wed, 9 Jan 2019 14:34:45 +0300
Subject: [PATCH] Removed obsolete delay modules

---
 DynDelay.v    | 53 ---------------------------------------------------
 StaticDelay.v | 51 -------------------------------------------------
 2 files changed, 104 deletions(-)
 delete mode 100644 DynDelay.v
 delete mode 100644 StaticDelay.v

diff --git a/DynDelay.v b/DynDelay.v
deleted file mode 100644
index a95889f..0000000
--- a/DynDelay.v
+++ /dev/null
@@ -1,53 +0,0 @@
-//--------------------------------------------------------------------------------
-// DynDelay.v
-// Konstantin Pavlov, pavlovconst@gmail.com
-//--------------------------------------------------------------------------------
-
-// INFO --------------------------------------------------------------------------------
-//  Dynamic delay for arbitrary signal
-//  
-
-/* --- INSTANTIATION TEMPLATE BEGIN ---
-
-DynDelay DD1 (
-	.clk(  ),
-    .nrst( 1'b1 ),
-	.in(  ),
-	.sel(  ),
-	.out(  )
-	);
-defparam DD1.LENGTH = 8;
-
---- INSTANTIATION TEMPLATE END ---*/
-
-
-//(* keep_hierarchy = "yes" *)
-module DynDelay(clk,nrst,in,sel,out);
-
-input wire clk;
-input wire nrst;
-input wire in;
-input wire [(LENGTH-1):0] sel;	// output selector
-output reg out;
-
-parameter LENGTH = 8;
-
-(* keep = "true" *) reg [(LENGTH-1):0] data = 0;
-
-integer i;
-
-always @ (posedge clk) begin
-	if (~nrst) begin
-		data[(LENGTH-1):0] <= 0;
-		out <= 0;
-	end
-	else begin
-		data[0] <= in;
-		for (i=1; i<LENGTH; i=i+1) begin
-			data[i] <= data[i-1];
-		end
-		out <= data[sel[(LENGTH-1):0]];
-	end
-end
-
-endmodule
\ No newline at end of file
diff --git a/StaticDelay.v b/StaticDelay.v
deleted file mode 100644
index d6a2ec5..0000000
--- a/StaticDelay.v
+++ /dev/null
@@ -1,51 +0,0 @@
-//--------------------------------------------------------------------------------
-// StaticDelay.v
-// Konstantin Pavlov, pavlovconst@gmail.com
-//--------------------------------------------------------------------------------
-
-// INFO --------------------------------------------------------------------------------
-//  Static Delay for arbitrary signal
-//  Also may serve as a FPGA clock domain input synchronizer - base technique to get rid of metastability issues
-//  TIP: Do not use reset on purpose of inferring Xilinx`s SRL16E primitive
-
-/* --- INSTANTIATION TEMPLATE BEGIN ---
-
-StaticDelay SD1 (
-    .clk(),
-    .nrst( 1'b1 ),
-    .in(),
-    .out()
-    );
-defparam SD1.LENGTH = 2;
-defparam SD1.WIDTH = 1;
-
---- INSTANTIATION TEMPLATE END ---*/
-
-
-//(* keep_hierarchy = "yes" *)
-module StaticDelay(clk,nrst,in,out);
-
-input wire clk;
-input wire nrst;
-input wire [(WIDTH-1):0] in;
-output wire [(WIDTH-1):0] out;
-
-parameter LENGTH = 2;   // length of each delay/synchronizer chain
-parameter WIDTH = 1;    // independent channels
-
-(* KEEP = "TRUE" *)(* ASYNC_REG = "TRUE" *) reg [(LENGTH*WIDTH-1):0] data = 0;
-
-always @ (posedge clk) begin
-	if (~nrst) begin
-		data[(LENGTH*WIDTH-1):0] <= 0;
-	end
-	else begin
-	data[(LENGTH*WIDTH-1):0] <= data[(LENGTH*WIDTH-1):0] << WIDTH;
-	data[(WIDTH-1):0] <= in[(WIDTH-1):0];
-end
-end
-
-assign
-    out[(WIDTH-1):0] = data[(LENGTH*WIDTH-1):((LENGTH-1)*WIDTH)];
-
-endmodule