From db847e6e7e241b183459be9703f725a233ef7270 Mon Sep 17 00:00:00 2001
From: Konstantin Pavlov <pavlovconst@gmail.com>
Date: Thu, 31 Mar 2022 20:20:15 +0300
Subject: [PATCH] Added RAM templates

---
 edge_detect.sv                            |  0
 true_dual_port_write_first_2_clock_ram.sv | 45 ++++++-----
 true_single_port_write_first_ram.sv       | 93 +++++++++++++++++++++++
 3 files changed, 118 insertions(+), 20 deletions(-)
 mode change 100644 => 100755 edge_detect.sv
 create mode 100755 true_single_port_write_first_ram.sv

diff --git a/edge_detect.sv b/edge_detect.sv
old mode 100644
new mode 100755
diff --git a/true_dual_port_write_first_2_clock_ram.sv b/true_dual_port_write_first_2_clock_ram.sv
index 4cf9ccd..42bc42b 100755
--- a/true_dual_port_write_first_2_clock_ram.sv
+++ b/true_dual_port_write_first_2_clock_ram.sv
@@ -1,5 +1,6 @@
 //------------------------------------------------------------------------------
 // true_dual_port_write_first_2_clock_ram.sv
+// published as part of https://github.com/pConst/basic_verilog
 // Konstantin Pavlov, pavlovconst@gmail.com
 //------------------------------------------------------------------------------
 
@@ -14,8 +15,9 @@
 true_dual_port_write_first_2_clock_ram #(
   .RAM_WIDTH( DATA_W ),
   .RAM_DEPTH( DEPTH ),
+  .RAM_STYLE( "init.mem" ),  // "block","register","M10K","logic",...
   .INIT_FILE( "" )
-) bram (
+) DR1 (
   .clka( w_clk ),
   .addra( w_ptr[DEPTH_W-1:0] ),
   .ena( w_req ),
@@ -37,6 +39,7 @@ true_dual_port_write_first_2_clock_ram #(
 module true_dual_port_write_first_2_clock_ram #( parameter
   RAM_WIDTH = 16,
   RAM_DEPTH = 8,
+  RAM_STYLE = "",
   INIT_FILE = ""
 )(
   input clka,
@@ -54,26 +57,33 @@ module true_dual_port_write_first_2_clock_ram #( parameter
   output [RAM_WIDTH-1:0] doutb
 );
 
+  // Xilinx:
+  // ram_style = "{ auto | block | distributed | register | ultra }"
+  // "ram_style" is equivalent to "ramstyle" in Vivado
 
-
-  logic [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
-  logic [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
-  logic [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
+  // Altera:
+  // ramstyle = "{ logic | M9K | MLAB }" and other variants
 
   // ONLY FOR QUARTUS IDE
   // You can provide initialization in convinient .mif format
-  //(* ram_init_file = INIT_FILE *) logic [RAM_WIDTH-1:0] BRAM [RAM_DEPTH-1:0];
+  //(* ram_init_file = INIT_FILE *) logic [RAM_WIDTH-1:0] data_mem [RAM_DEPTH-1:0];
+
+  (* ramstyle = RAM_STYLE *) logic [RAM_WIDTH-1:0] data_mem [RAM_DEPTH-1:0];
+
+
+  logic [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
+  logic [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
 
   // either initializes the memory values to a specified file or to all zeros
   generate
     if (INIT_FILE != "") begin: use_init_file
       initial
-        $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH-1);
+        $readmemh(INIT_FILE, data_mem, 0, RAM_DEPTH-1);
     end else begin: init_bram_to_zero
-      integer ram_index;
+      integer i;
       initial begin
-        for (ram_index=0; ram_index<RAM_DEPTH; ram_index=ram_index+1 ) begin
-          BRAM[ram_index] = {RAM_WIDTH{1'b0}};
+        for (i=0; i<RAM_DEPTH; i=i+1 ) begin
+          data_mem[i] = {RAM_WIDTH{1'b0}};
         end
       end
     end
@@ -82,10 +92,10 @@ module true_dual_port_write_first_2_clock_ram #( parameter
   always @(posedge clka) begin
     if (ena) begin
       if (wea) begin
-        BRAM[addra] <= dina;
+        data_mem[addra] <= dina;
         ram_data_a <= dina;
       end else begin
-        ram_data_a <= BRAM[addra];
+        ram_data_a <= data_mem[addra];
       end
     end
   end
@@ -93,10 +103,10 @@ module true_dual_port_write_first_2_clock_ram #( parameter
   always @(posedge clkb) begin
     if (enb) begin
       if (web) begin
-        BRAM[addrb] <= dinb;
+        data_mem[addrb] <= dinb;
         ram_data_b <= dinb;
       end else begin
-        ram_data_b <= BRAM[addrb];
+        ram_data_b <= data_mem[addrb];
       end
     end
   end
@@ -105,12 +115,7 @@ module true_dual_port_write_first_2_clock_ram #( parameter
   assign douta = ram_data_a;
   assign doutb = ram_data_b;
 
-  // calculates the address width based on specified RAM depth
-  function integer clogb2;
-    input integer depth;
-      for (clogb2=0; depth>0; clogb2=clogb2+1)
-        depth = depth >> 1;
-  endfunction
+  `include "clogb2.svh"
 
 endmodule
 
diff --git a/true_single_port_write_first_ram.sv b/true_single_port_write_first_ram.sv
new file mode 100755
index 0000000..1071802
--- /dev/null
+++ b/true_single_port_write_first_ram.sv
@@ -0,0 +1,93 @@
+//------------------------------------------------------------------------------
+// true_single_port_write_first_ram.sv
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  This is single port RAM/ROM module
+//  Also tested for Quartus IDE to automatically infer block memories
+//
+
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+true_single_port_write_first_ram #(
+  .RAM_WIDTH( DATA_W ),
+  .RAM_DEPTH( DEPTH ),
+  .RAM_STYLE( "init.mem" ),  // "block","register","M10K","logic",...
+  .INIT_FILE( "" )
+) SR1 (
+  .clka( w_clk ),
+  .addra( w_ptr[DEPTH_W-1:0] ),
+  .ena( w_req ),
+  .wea( 1'b1 ),
+  .dina( w_data[DATA_W-1:0] ),
+  .douta(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module true_single_port_write_first_ram #( parameter
+  RAM_WIDTH = 16,
+  RAM_DEPTH = 8,
+  RAM_STYLE = "",
+  INIT_FILE = ""
+)(
+  input clka,
+  input [clogb2(RAM_DEPTH-1)-1:0] addra,
+  input ena,
+  input wea,
+  input [RAM_WIDTH-1:0] dina,
+  output [RAM_WIDTH-1:0] douta
+);
+
+  // Xilinx:
+  // ram_style = "{ auto | block | distributed | register | ultra }"
+  // "ram_style" is equivalent to "ramstyle" in Vivado
+
+  // Altera:
+  // ramstyle = "{ logic | M9K | MLAB }" and other variants
+
+  // ONLY FOR QUARTUS IDE
+  // You can provide initialization in convinient .mif format
+  //(* ram_init_file = INIT_FILE *) logic [RAM_WIDTH-1:0] data_mem [RAM_DEPTH-1:0];
+
+  (* ramstyle = RAM_STYLE *) logic [RAM_WIDTH-1:0] data_mem [RAM_DEPTH-1:0];
+
+
+  logic [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
+
+  // either initializes the memory values to a specified file or to all zeros
+  generate
+    if (INIT_FILE != "") begin: use_init_file
+      initial
+        $readmemh(INIT_FILE, data_mem, 0, RAM_DEPTH-1);
+    end else begin: init_bram_to_zero
+      integer i;
+      initial begin
+        for (i=0; i<RAM_DEPTH; i=i+1 ) begin
+          data_mem[i] = {RAM_WIDTH{1'b0}};
+        end
+      end
+    end
+  endgenerate
+
+  always @(posedge clka) begin
+    if (ena) begin
+      if (wea) begin
+        data_mem[addra] <= dina;
+        ram_data_a <= dina;
+      end else begin
+        ram_data_a <= data_mem[addra];
+      end
+    end
+  end
+
+  // no output register
+  assign douta = ram_data_a;
+
+  `include "clogb2.svh"
+
+endmodule
+