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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

Change some pins to I and IO for convinience

This commit is contained in:
Konstantin Pavlov 2024-07-02 16:01:04 +03:00
parent 955efdf32d
commit e1412c080b

View File

@ -69,12 +69,12 @@ module main(
input [5:0] ck_an_n,
// Digital I/O On Outer Analog Header
output [5:0] ck_a,
inout [5:0] ck_a,
// Digital I/O On Inner Analog Header
//
// Digital I/O Low
output [13:0] ck_io_low,
input [13:0] ck_io_low,
// Digital I/O High
output [41:26] ck_io_high,
@ -87,9 +87,16 @@ module main(
output ck_ioa
);
`VIVADO_MODULE_HEADER
//`VIVADO_MODULE_HEADER
// convinience rename ==========================================================
logic [13:0] hdr_in;
assign hdr_in[13:0] = ck_io_low[13:0];
logic [15:0] hdr_out;
assign ck_io_high[41:26] = hdr_out[15:0];
// clocks ======================================================================
logic sys_pll_locked; // asyn