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README update
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Konstantin Pavlov
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README.md
114
README.md
@ -26,7 +26,7 @@ For your convinience I`ve tagged some sources by their "difficulty":
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If you are a beginner in HW design - you may want to start exploring :green_circle: code first.
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Almost every source file in the repository contains detailed description and instantiation template!
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| USAGE | DIRECTORY | DESCRIPTION |
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| | DIRECTORY | DESCRIPTION |
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|---------------|--------------|-------------|
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| | Advanced Synthesis Cookbook/ | useful code from Altera's cookbook |
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| | KCPSM6_Release9_30Sept14/ | Xilinx's Picoblaze soft processor sources |
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@ -43,64 +43,64 @@ Almost every source file in the repository contains detailed description and ins
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| :red_circle: | scripts_for_xilinx_hls/ | useful scripts for compiling for Xilinx HLS |
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| | xpm | Xilinx parametrizable macros sources |
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| USAGE | FILE | DESCRIPTION |
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|----------------|--------------------|-------------|
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| | adder_tree.sv | adding multiple values together in parallel |
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| | axi4l_logger.sv | |
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| :green_circle: | bin2gray.sv | combinational Gray code to binary converter |
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| | bin2pos.sv | converts binary coded value to positional (one-hot) code |
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| | cdc_data.sv | |
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| | cdc_strobe.sv | |
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| :green_circle: | clk_divider.sv | wide reference clock divider |
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| | clogb2.svh | |
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| :green_circle: | debounce.v | two-cycle debounce for input buttons |
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| :green_circle: | delay.sv | useful module to make static delays or to synchronize across clock domains |
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| | delayed_event.sv | |
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| | dynamic_delay.sv | dynamic delay for arbitrary input signal |
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| :green_circle: | edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge |
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| | encoder.v | digital encoder input logic module |
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| :red_circle: | fast_counter.sv | |
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| | fifo_combiner.sv | |
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| | fifo_operator.sv | |
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| | FILE | DESCRIPTION |
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|----------------|-------------------- |-------------|
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| | adder_tree.sv | adding multiple values together in parallel |
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| | axi4l_logger.sv | sniffs all AXI transactions and stores address and data to fifo |
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| :green_circle: | bin2gray.sv | combinational Gray code to binary converter |
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| | bin2pos.sv | converts binary coded value to positional (one-hot) code |
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| | cdc_data.sv | standard two-stage data synchronizer |
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| | cdc_strobe.sv | clock crossing synchronizer for one-cycle strobes |
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| :green_circle: | clk_divider.sv | wide reference clock divider |
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| | clogb2.svh | calculates counter/address width based on specified vector/RAM depth |
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| :green_circle: | debounce.v | two-cycle debounce for input buttons |
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| :green_circle: | delay.sv | useful module to make static delays or to synchronize across clock domains |
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| | delayed_event.sv | generates delayed pulse one clock width |
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| | dynamic_delay.sv | dynamic delay for arbitrary input signal |
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| :green_circle: | edge_detect.sv | combinational edge detector, gives one-tick pulses on every signal edge |
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| | encoder.v | digital encoder input logic module |
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| :red_circle: | fast_counter.sv | synthetic counter |
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| | fifo_combiner.sv | accumulates data words from multiple FIFOs to a single output FIFO |
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| | fifo_operator.sv | performs custom operation on data words from multiple FIFOs and stores result to a single output FIFO |
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| :red_circle: | fifo_single_clock_ram_*.sv | single-clock FIFO buffer (queue) implementation |
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| :red_circle: | fifo_single_clock_reg_*.sv | single-clock FIFO buffer (queue) implementation |
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| :green_circle: | gray2bin.sv | combinational binary to Gray code converter |
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| :red_circle: | gray_functions.vh | |
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| :green_circle: | hex2ascii.sv | |
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| | leave_one_hot.sv | combinational module that leaves only lowest hot bit |
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| | lifo.sv | single-clock LIFO buffer (stack) implementation |
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| | main_tb.sv | basic testbench template |
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| | moving_average.sv | |
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| | pack_unpack_array.v | |
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| | pattern_detect.sv | |
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| | pdm_modulator.sv | |
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| | pos2bin.sv | converts positional (one-hot) value to binary representation |
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| | prbs_gen_chk.sv | PRBS pattern generator or checker |
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| | preview_fifo.sv | |
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| | priority_enc.sv | |
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| | pulse_gen.sv | generates pulses with given width and delay |
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| | pulse_stretch.sv | configurable pulse stretcher/extender module |
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| | pwm_modulator.sv | |
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| :red_circle: | read_ahead_buf.sv | |
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| | reset_set.sv | SR trigger variant w/o metastable state, set dominates here |
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| | reset_set_comb.sv | |
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| | reverse_bytes.sv | reverses bytes order within multi-byte array |
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| | reverse_dimensions.sv | |
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| | reverse_vector.sv | reverses signal order within multi-bit bus |
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| | round_robin_enc.sv | |
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| | round_robin_performance_enc.sv | |
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| | set_reset.sv | SR trigger variant w/o metastable state, reset dominates here |
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| | set_reset_comb.sv | |
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| | sim_clk_gen.sv | |
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| :red_circle: | soft_latch.sv | |
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| | spi_master.sv | universal spi master module |
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| :red_circle: | true_dual_port_write_first_2_clock_ram.sv | |
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| :red_circle: | true_single_port_write_first_ram.sv | |
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| | uart_debug_printer.sv | |
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| :green_circle: | uart_rx.sv | straightforward yet simple UART receiver |
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| | uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs |
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| :green_circle: | uart_tx.sv | straightforward yet simple UART transmitter |
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| | uart_tx_shifter.sv | UART-like transmitter shifter for simple synchronous messaging inside the FPGA or between FPGAs |
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| :green_circle: | gray2bin.sv | combinational binary to Gray code converter |
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| :red_circle: | gray_functions.vh | Gray code parametrizable converter functions |
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| :green_circle: | hex2ascii.sv | converts 4-bit binary nibble to 8-bit human-readable ASCII char |
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| | leave_one_hot.sv | combinational module that leaves only lowest hot bit |
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| | lifo.sv | single-clock LIFO buffer (stack) implementation |
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| | main_tb.sv | basic testbench template |
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| | moving_average.sv | Simple moving average implementation |
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| | pack_unpack_array.v | macros for packing and unpacking 2D and 3D vectors in Verilog-2001 |
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| | pattern_detect.sv | detects data pattern specified |
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| | pdm_modulator.sv | pulse density modulation generator module |
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| | pos2bin.sv | converts positional (one-hot) value to binary representation |
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| | prbs_gen_chk.sv | PRBS pattern generator or checker |
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| | preview_fifo.sv | FIFO with an ability to be read 0, 1 or 2 words at once |
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| | priority_enc.sv | combinational priority_encoder |
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| | pulse_gen.sv | generates pulses with given width and delay |
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| | pulse_stretch.sv | configurable pulse stretcher/extender module |
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| | pwm_modulator.sv | pulse width modulation generator |
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| :red_circle: | read_ahead_buf.sv | substitutes fifo read port and performs fifo data update at the same clock cycle |
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| | reset_set.sv | SR trigger variant w/o metastable state, set dominates here |
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| | reset_set_comb.sv | synchronous SR trigger, but has a combinational output |
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| | reverse_bytes.sv | reverses bytes order within multi-byte array |
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| | reverse_dimensions.sv | reverses dimension order in SystemVerilog 2D vector |
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| | reverse_vector.sv | reverses signal order within multi-bit bus |
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| | round_robin_enc.sv | round robin combinational encoder |
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| | round_robin_performance_enc.sv | performance improved round robin encoder |
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| | set_reset.sv | SR trigger variant w/o metastable state, reset dominates here |
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| | set_reset_comb.sv | synchronous SR trigger, but has a combinational output |
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| | sim_clk_gen.sv | testbench clock generator |
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| :red_circle: | soft_latch.sv | combinational data hold circuit |
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| | spi_master.sv | universal spi master module |
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| :red_circle: | true_dual_port_write_first_2_clock_ram.sv | double port RAM/ROM module |
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| :red_circle: | true_single_port_write_first_ram.sv | single port RAM/ROM module |
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| | uart_debug_printer.sv | debug data printer to UART terminal |
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| :green_circle: | uart_rx.sv | straightforward yet simple UART receiver |
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| | uart_rx_shifter.sv | UART-like receiver shifter for simple synchronous messaging inside the FPGA or between FPGAs |
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| :green_circle: | uart_tx.sv | straightforward yet simple UART transmitter |
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| | uart_tx_shifter.sv | UART-like transmitter shifter for simple synchronous messaging inside the FPGA or between FPGAs |
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Also added testbenches for selected modules.
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