Update formatting

lifo.sv

@@ -47,8 +47,6 @@ module lifo #( parameter
                                   // "FALSE" - normal fifo mode
 
   DEPTH = 8,                      // max elements count == DEPTH, DEPTH MUST be power of 2
-  DEPTH_W = $clog2(DEPTH)+1,      // elements counter width, extra bit to store
-                                  // "fifo full" state, see cnt[] variable comments
 
   DATA_W = 32                     // data field width
 )(
@@ -72,26 +70,31 @@ module lifo #( parameter
   output logic fail
 );
 
-// lifo data
-logic [DEPTH-1:0][DATA_W-1:0] data = '0;
-
-// data output buffer for normal fifo mode
-logic [DATA_W-1:0] data_buf = '0;
-
-// cnt[] vector always holds lifo elements count
-// data[cnt[]] points to the first empty lifo slot
-// when lifo is full data[cnt[]] points "outside" of data[]
-
-// filtered requests
-logic w_req_f;
-assign w_req_f = w_req && ~full;
-
-logic r_req_f;
-assign r_req_f = r_req && ~empty;
+  // elements counter width, extra bit to store
+  // "fifo full" state, see cnt[] variable comments
+  localparam DEPTH_W = $clog2(DEPTH+1);
 
 
-integer i;
-always_ff @(posedge clk) begin
+  // lifo data
+  logic [DEPTH-1:0][DATA_W-1:0] data = '0;
+
+  // data output buffer for normal fifo mode
+  logic [DATA_W-1:0] data_buf = '0;
+
+  // cnt[] vector always holds lifo elements count
+  // data[cnt[]] points to the first empty lifo slot
+  // when lifo is full data[cnt[]] points "outside" of data[]
+
+  // filtered requests
+  logic w_req_f;
+  assign w_req_f = w_req && ~full;
+
+  logic r_req_f;
+  assign r_req_f = r_req && ~empty;
+
+
+  integer i;
+  always_ff @(posedge clk) begin
     if ( ~nrst ) begin
       data <= '0;
       cnt[DEPTH_W-1:0] <= '0;
@@ -123,10 +126,10 @@ always_ff @(posedge clk) begin
         data_buf[DATA_W-1:0] <= data[0];
       end
     end
-end
+  end
 
 
-always_comb begin
+  always_comb begin
     empty = ( cnt[DEPTH_W-1:0] == '0 );
     full = ( cnt[DEPTH_W-1:0] == DEPTH );
 
@@ -142,6 +145,7 @@ always_comb begin
 
     fail = ( empty && r_req ) ||
            ( full && w_req );
-end
+  end
 
 endmodule
+