Added Fmax test projects for Quartus and for Vivado

example_projects/quartus_fmax_test_prj_template_v3/.gitignore

@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------
+# .gitignore for Intel Quartus
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# INFO ------------------------------------------------------------------------
+# rename the file to ".gitignore" and place into your Quartus project directory
+#
+
+
+# junk files
+*.qws
+*_assignment_defaults.qdf
+c5_pin_model_dump.txt
+*.ipregen.rpt
+*_summary.csv
+*_early_pwr.csv
+
+# junk directories
+/.qsys_edit
+/db
+/incremental_db
+/greybox_tmp
+
+# design space explorer
+/dse
+dse1_base.qpf
+dse1_base.qsf
+*.dse.rpt
+*.archive.rpt
+
+/out
+

example_projects/quartus_fmax_test_prj_template_v3/clean_quartus.bat

@@ -0,0 +1,44 @@
+@echo off
+rem ------------------------------------------------------------------------------
+rem  clean_quartus.bat
+rem  Konstantin Pavlov, pavlovconst@gmail.com
+rem ------------------------------------------------------------------------------
+
+rem   Use this file as a boilerplate for your custom clean script
+rem   for Quartus projects
+
+SET PROJ=test
+
+rem Common junk files
+del /s /q .\%PROJ%.qws
+del /s /q .\c5_pin_model_dump.txt
+del /s /q .\%PROJ%.ipregen.rpt
+del /s /f /q .\.qsys_edit\*
+rmdir /s /q .\.qsys_edit\
+del /s /q .\%PROJ%_assignment_defaults.qdf
+
+rem Compilation databases
+del /s /f /q .\db\*
+rmdir /s /q .\db\
+del /s /f /q .\incremental_db\*
+rmdir /s /q .\incremental_db\
+del /s /f /q .\greybox_tmp\*
+rmdir /s /q .\greybox_tmp\
+
+rem Output directory
+del /s /f /q .\out\*
+rmdir /s /q .\out\
+
+rem Design space explorer files
+del /s /f /q .\dse\*
+rmdir /s /q .\dse\
+del /s /q .\dse1_base.qpf
+del /s /q .\dse1_base.qsf
+del /s /q .\%PROJ%.dse.rpt
+del /s /q .\%PROJ%.archive.rpt
+
+rem Early power estimator files
+del /s /q .\%PROJ%_early_pwr.csv
+
+pause
+goto :eof

example_projects/quartus_fmax_test_prj_template_v3/src/clk_divider.sv

@@ -0,0 +1,43 @@
+//------------------------------------------------------------------------------
+// clk_divider.sv
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  Divides main clock to get derivative slower synchronous clocks
+//
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+clk_divider #(
+  .WIDTH( 32 )
+) CD1 (
+  .clk( clk ),
+  .nrst( 1'b1 ),
+  .ena( 1'b1 ),
+  .out(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module clk_divider #( parameter
+  WIDTH = 32
+)(
+  input clk,
+  input nrst,
+  input ena,
+  output logic [(WIDTH-1):0] out = '0
+);
+
+
+always_ff @(posedge clk) begin
+  if ( ~nrst ) begin
+    out[(WIDTH-1):0] <= '0;
+  end else if (ena) begin
+    out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
+  end
+end
+
+endmodule

example_projects/quartus_fmax_test_prj_template_v3/src/main.sdc

@@ -0,0 +1,6 @@
+
+# main reference clock, 500 MHz
+create_clock -period 2.000 -waveform { 0.000 1.000 } [get_ports {clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty

example_projects/quartus_fmax_test_prj_template_v3/src/main.sv

@@ -0,0 +1,68 @@
+//------------------------------------------------------------------------------
+// main.sv
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+// minimal FMAX test project template, v3
+//
+// - use this as a boilerplate for fast prototyping and FMAX investigating
+// - inputs and outputs are registered to allow valid timequest output
+//   even if your custom logic/IPs have combinational outputs
+// - SDC constraint file assigns clk to 500MHz to force fitter to synthesize
+//   the fastest possible circuit
+//
+
+`define WIDTH 64
+
+module main(
+
+  input clk,
+  input nrst,
+
+  input [`WIDTH-1:0] in_data,
+  output logic [`WIDTH-1:0] out_data
+);
+
+// input registers
+logic [`WIDTH-1:0] in_data_reg = '0;
+always_ff @(posedge clk) begin
+  if( ~nrst ) begin
+    in_data_reg[`WIDTH-1:0] <= '0;
+  end else begin
+    in_data_reg[`WIDTH-1:0] <= in_data;
+  end
+end
+
+logic [`WIDTH-1:0] out_data_comb = '0;
+
+// place your test logic here ==================================================
+
+logic [31:0] div_clk;
+clk_divider #(
+  .WIDTH( 32 )
+) cd1 (
+  .clk( clk ),
+  .nrst( nrst ),
+  .ena( 1'b1 ),
+  .out( div_clk[31:0] )
+);
+
+always_comb begin
+  out_data_comb[`WIDTH-1:0] <= in_data_reg[`WIDTH-1:0] ^ div_clk[31:0];
+end
+
+
+// =============================================================================
+
+// output registers
+always_ff @(posedge clk) begin
+  if( ~nrst ) begin
+    out_data[`WIDTH-1:0] <= '0;
+  end else begin
+    out_data[`WIDTH-1:0] <= out_data_comb[`WIDTH-1:0];
+  end
+end
+
+endmodule

example_projects/quartus_fmax_test_prj_template_v3/test.qpf

@@ -0,0 +1 @@
+PROJECT_REVISION = "test"

example_projects/quartus_fmax_test_prj_template_v3/test.qsf

@@ -0,0 +1,22 @@
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CGXFC4C7F27C8
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
+
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name TOP_LEVEL_ENTITY main
+
+
+set_global_assignment -name SYSTEMVERILOG_FILE ./src/main.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ./src/clk_divider.sv
+set_global_assignment -name SDC_FILE ./src/main.sdc
+
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

example_projects/vivado_fmax_test_prj_template_v3/.gitignore

@@ -0,0 +1,11 @@
+
+
+*.cache
+*.hw
+*.runs
+*.sim
+.Xil
+
+*.jou
+*.log
+

example_projects/vivado_fmax_test_prj_template_v3/hard_clean_vivado.bat

@@ -0,0 +1,31 @@
+@echo off
+rem ------------------------------------------------------------------------------
+rem  clean.bat
+rem  Konstantin Pavlov, pavlovconst@gmail.com
+rem ------------------------------------------------------------------------------
+
+rem Use this file as a boilerplate for your custom clean script
+rem for Vivado/Vitis projects
+
+SET PROJ=test
+
+del /s /f /q .\%PROJ%.cache\*
+rmdir /s /q .\%PROJ%.cache\
+
+del /s /f /q .\%PROJ%.hw\*
+rmdir /s /q .\%PROJ%.hw\
+
+del /s /f /q .\%PROJ%.runs\*
+rmdir /s /q .\%PROJ%.runs\
+
+del /s /f /q .\%PROJ%.sim\*
+rmdir /s /q .\%PROJ%.sim\
+
+del /s /f /q .\.Xil\*
+rmdir /s /q .\.Xil\
+
+del /s /f /q .\*.jou
+del /s /f /q .\*.log
+
+pause
+exit

example_projects/vivado_fmax_test_prj_template_v3/scripts/allow_undefined_ports.tcl

@@ -0,0 +1,14 @@
+#------------------------------------------------------------------------------
+# allow_undefined_ports.tcl
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+# INFO ------------------------------------------------------------------------
+# Use this script for Xilinx Vivado environment to allow generation of test
+# projects with undefines pins (that will eventually have DEFAULT positional
+# and electrical standard constraints)
+#
+# Place this script as a pre-tcl-script for "Generate bitstream" step
+
+set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
+set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

example_projects/vivado_fmax_test_prj_template_v3/scripts/get_fmax_vivado.tcl

@@ -0,0 +1,18 @@
+#------------------------------------------------------------------------------
+# get_fmax_vivado.tcl
+# published as part of https://github.com/pConst/basic_verilog
+# Konstantin Pavlov, pavlovconst@gmail.com
+#------------------------------------------------------------------------------
+
+
+fmax 1000
+
+# compuiting fmax, in MHz, given target clock in MHz
+proc fmax {target_clock} {
+    open_run impl_1
+    puts [ join [ list \
+        [expr round(1e3/((1e3/$target_clock)-[get_property SLACK [get_timing_paths]]))] \
+        " MHz" ] "" ]
+    puts ""
+}
+

example_projects/vivado_fmax_test_prj_template_v3/src/clk_divider.sv

@@ -0,0 +1,43 @@
+//------------------------------------------------------------------------------
+// clk_divider.sv
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+//  Divides main clock to get derivative slower synchronous clocks
+//
+
+/* --- INSTANTIATION TEMPLATE BEGIN ---
+
+clk_divider #(
+  .WIDTH( 32 )
+) CD1 (
+  .clk( clk ),
+  .nrst( 1'b1 ),
+  .ena( 1'b1 ),
+  .out(  )
+);
+
+--- INSTANTIATION TEMPLATE END ---*/
+
+
+module clk_divider #( parameter
+  WIDTH = 32
+)(
+  input clk,
+  input nrst,
+  input ena,
+  output logic [(WIDTH-1):0] out = '0
+);
+
+
+always_ff @(posedge clk) begin
+  if ( ~nrst ) begin
+    out[(WIDTH-1):0] <= '0;
+  end else if (ena) begin
+    out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
+  end
+end
+
+endmodule

example_projects/vivado_fmax_test_prj_template_v3/src/main.sv

@@ -0,0 +1,68 @@
+//------------------------------------------------------------------------------
+// main.sv
+// published as part of https://github.com/pConst/basic_verilog
+// Konstantin Pavlov, pavlovconst@gmail.com
+//------------------------------------------------------------------------------
+
+// INFO ------------------------------------------------------------------------
+// minimal FMAX test project template, v3
+//
+// - use this as a boilerplate for fast prototyping and FMAX investigating
+// - inputs and outputs are registered to allow valid timequest output
+//   even if your custom logic/IPs have combinational outputs
+// - SDC constraint file assigns clk to 500MHz to force fitter to synthesize
+//   the fastest possible circuit
+//
+
+`define WIDTH 64
+
+module main(
+
+  input clk,
+  input nrst,
+
+  input [`WIDTH-1:0] in_data,
+  output logic [`WIDTH-1:0] out_data
+);
+
+// input registers
+logic [`WIDTH-1:0] in_data_reg = '0;
+always_ff @(posedge clk) begin
+  if( ~nrst ) begin
+    in_data_reg[`WIDTH-1:0] <= '0;
+  end else begin
+    in_data_reg[`WIDTH-1:0] <= in_data;
+  end
+end
+
+logic [`WIDTH-1:0] out_data_comb = '0;
+
+// place your test logic here ==================================================
+
+logic [31:0] div_clk;
+clk_divider #(
+  .WIDTH( 32 )
+) cd1 (
+  .clk( clk ),
+  .nrst( nrst ),
+  .ena( 1'b1 ),
+  .out( div_clk[31:0] )
+);
+
+always_comb begin
+  out_data_comb[`WIDTH-1:0] <= in_data_reg[`WIDTH-1:0] ^ div_clk[31:0];
+end
+
+
+// =============================================================================
+
+// output registers
+always_ff @(posedge clk) begin
+  if( ~nrst ) begin
+    out_data[`WIDTH-1:0] <= '0;
+  end else begin
+    out_data[`WIDTH-1:0] <= out_data_comb[`WIDTH-1:0];
+  end
+end
+
+endmodule

example_projects/vivado_fmax_test_prj_template_v3/src/timing.xdc

@@ -0,0 +1,3 @@
+
+# main reference clock, 1000 MHz requested
+create_clock -name clk -period 1.000 -waveform {0.000 0.500} [get_ports { clk }]

example_projects/vivado_fmax_test_prj_template_v3/test.xpr

@@ -0,0 +1,190 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2019.2 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="44" Path="J:/basic_verilog/example_projects/vivado_fmax_test_prj_template_v2/test.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="551196a343084fe495b8bdfd057029bd"/>
+    <Option Name="Part" Val="xa7a12tcsg325-2I"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSANumComputeUnits" Val="16"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="6"/>
+    <Option Name="WTModelSimExportSim" Val="6"/>
+    <Option Name="WTQuestaExportSim" Val="6"/>
+    <Option Name="WTIesExportSim" Val="6"/>
+    <Option Name="WTVcsExportSim" Val="6"/>
+    <Option Name="WTRivieraExportSim" Val="6"/>
+    <Option Name="WTActivehdlExportSim" Val="6"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/src/clk_divider.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/src/main.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="main"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/src/timing.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/src/timing.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="main"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <File Path="$PPRDIR/scripts/allow_undefined_ports.tcl">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+          <Attr Name="UsedInSteps" Val="impl_1;WRITE_BITSTREAM;TCL.PRE"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="11">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xa7a12tcsg325-2I" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xa7a12tcsg325-2I" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design" EnableStepBool="1"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream" PreStepTclHook="$PPRDIR/scripts/allow_undefined_ports.tcl"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="No Reports" Flow="Vivado Implementation 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"/>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"/>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"/>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"/>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"/>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>