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Fixes for delayed_event module
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@ -15,13 +15,13 @@
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// |
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// | <---------- DELAY -------->
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// | ___
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// |___,___,___,___,___,___,___,___,___,___| |___,___,___, on
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// |___,___,___,___,___,___,___,___,___,___| |___,___,___, on_event
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// |
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// |___,___,___,___,___,___,___,___,___,___,
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// | , , , , , , , , , |___,___,___,___, before_event
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// | ,___,___,___,___,___,___,___,
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// |___,___,___| , , , , , , |___,___,___,___, before_event
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// |
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// |___,___, ___,___,___,___,
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// | , |___,___,___,___,___,___,___,___| , , , , after_event
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// |___,___,___ ___,___,___,___,
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// | , , |___,___,___,___,___,___,___| , , , , after_event
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// |
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//
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@ -42,9 +42,9 @@ delayed_event #(
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--- INSTANTIATION TEMPLATE END ---*/
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module pulse_gen #( parameter
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module delayed_event #( parameter
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DELAY = 32,
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CNTR_WIDTH = $clog(DELAY)
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CNTR_WIDTH = $clog2(DELAY)
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)(
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input clk, // system clock
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input nrst, // negative reset
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@ -56,7 +56,7 @@ module pulse_gen #( parameter
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);
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logic [CNTR_WIDTH-1:0] seq_cntr = DELAY;
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logic [CNTR_WIDTH-1:0] seq_cntr = CNTR_WIDTH'(DELAY);
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logic seq_cntr_is_0;
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assign seq_cntr_is_0 = (seq_cntr[CNTR_WIDTH-1:0]=='0);
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