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Fixes for delayed_event module

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Konstantin Pavlov 2020-11-03 11:23:37 +03:00
parent 2d2041a663
commit f5f3d32951
1 changed files with 8 additions and 8 deletions
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16
delayed_event.sv
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@ -15,13 +15,13 @@
// | // |
// | <---------- DELAY --------> // | <---------- DELAY -------->
// | ___ // | ___
// |___,___,___,___,___,___,___,___,___,___| |___,___,___, on // |___,___,___,___,___,___,___,___,___,___| |___,___,___, on_event
// | // |
// |___,___,___,___,___,___,___,___,___,___, // | ,___,___,___,___,___,___,___,
// | , , , , , , , , , |___,___,___,___, before_event // |___,___,___| , , , , , , |___,___,___,___, before_event
// | // |
// |___,___, ___,___,___,___, // |___,___,___ ___,___,___,___,
// | , |___,___,___,___,___,___,___,___| , , , , after_event // | , , |___,___,___,___,___,___,___| , , , , after_event
// | // |
// //
@ -42,9 +42,9 @@ delayed_event #(
--- INSTANTIATION TEMPLATE END ---*/ --- INSTANTIATION TEMPLATE END ---*/
module pulse_gen #( parameter module delayed_event #( parameter
DELAY = 32, DELAY = 32,
CNTR_WIDTH = $clog(DELAY) CNTR_WIDTH = $clog2(DELAY)
)( )(
input clk, // system clock input clk, // system clock
input nrst, // negative reset input nrst, // negative reset
@ -56,7 +56,7 @@ module pulse_gen #( parameter
); );
logic [CNTR_WIDTH-1:0] seq_cntr = DELAY; logic [CNTR_WIDTH-1:0] seq_cntr = CNTR_WIDTH'(DELAY);
logic seq_cntr_is_0; logic seq_cntr_is_0;
assign seq_cntr_is_0 = (seq_cntr[CNTR_WIDTH-1:0]=='0); assign seq_cntr_is_0 = (seq_cntr[CNTR_WIDTH-1:0]=='0);