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Konstantin Pavlov 2018-08-01 07:00:37 +03:00
parent 829d84b4c7
commit f838698dda
4 changed files with 50 additions and 50 deletions
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16
ClkDivider.sv
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@ -1,9 +1,9 @@
//--------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// ClkDivider.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// INFO ------------------------------------------------------------------------
// Divides main clock to get derivative slower synchronous clocks
@ -30,11 +30,11 @@ module ClkDivider #(
always_ff @(posedge clk) begin
if ( ~nrst ) begin
out[(WIDTH-1):0] <= 0;
end else begin
out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
end
if ( ~nrst ) begin
out[(WIDTH-1):0] <= 0;
end else begin
out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
end
end
endmodule

23
ClkDivider.v
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@ -1,10 +1,11 @@
//--------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// ClkDivider.v
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Divides main clock to get derivative slower synchronous clocks
// INFO ------------------------------------------------------------------------
// Divides main clock to get derivative slower synchronous clocks
// See ClkDivider.sv file for SystemVerilog version of this module
/* --- INSTANTIATION TEMPLATE BEGIN ---
@ -28,12 +29,12 @@ output reg [(WIDTH-1):0] out = 0;
parameter WIDTH = 32;
always @ (posedge clk) begin
if (~nrst) begin
out[(WIDTH-1):0] <= 0;
end
else begin
out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
end
if (~nrst) begin
out[(WIDTH-1):0] <= 0;
end
else begin
out[(WIDTH-1):0] <= out[(WIDTH-1):0] + 1'b1;
end
end
endmodule
endmodule

26
EdgeDetect.sv
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@ -1,11 +1,11 @@
//--------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// EdgeDetect.sv
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Variable width edge detector
// One tick propagation time
// INFO ------------------------------------------------------------------------
// Variable width edge detector
// Features one tick propagation time
/* --- INSTANTIATION TEMPLATE BEGIN ---
@ -40,16 +40,16 @@ module EdgeDetect #(
logic [(WIDTH-1):0] in_prev = 0;
always_ff @(posedge clk) begin
if ( ~nrst ) begin
in_prev <= 0;
rising <= 0;
falling <= 0;
end
else begin
in_prev <= in;
if ( ~nrst ) begin
in_prev <= 0;
rising <= 0;
falling <= 0;
end
else begin
in_prev <= in;
rising[(WIDTH-1):0] <= in[(WIDTH-1):0] & ~in_prev[(WIDTH-1):0];
falling[(WIDTH-1):0] <= ~in[(WIDTH-1):0] & in_prev[(WIDTH-1):0];
end
end
end
assign both[(WIDTH-1):0] = rising[(WIDTH-1):0] | falling[(WIDTH-1):0];

35
EdgeDetect.v
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@ -1,11 +1,12 @@
//--------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// EdgeDetect.v
// Konstantin Pavlov, pavlovconst@gmail.com
//--------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// INFO --------------------------------------------------------------------------------
// Simply edge detector
// One tick propagation time
// INFO ------------------------------------------------------------------------
// Variable width edge detector
// One tick propagation time
// See EdgeDetect.sv file for SystemVerilog version of this module
/*EdgeDetect ED1 (
@ -32,20 +33,18 @@ output wire [(WIDTH-1):0] both;
parameter WIDTH = 1;
reg [(WIDTH-1):0] in_prev = 0;
always @ (posedge clk) begin
if (~nrst) begin
in_prev <= 0;
rising <= 0;
falling <= 0;
end
else begin
in_prev <= in;
rising[(WIDTH-1):0] <= in[(WIDTH-1):0] & ~in_prev[(WIDTH-1):0];
falling[(WIDTH-1):0] <= ~in[(WIDTH-1):0] & in_prev[(WIDTH-1):0];
end
if ( ~nrst ) begin
in_prev <= 0;
rising <= 0;
falling <= 0;
end
else begin
in_prev <= in;
rising[(WIDTH-1):0] <= in[(WIDTH-1):0] & ~in_prev[(WIDTH-1):0];
falling[(WIDTH-1):0] <= ~in[(WIDTH-1):0] & in_prev[(WIDTH-1):0];
end
end
assign