FPGA/basic_verilog
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6 Commits

Author SHA1 Message Date
Konstantin Pavlov
f74126e5d6 Minor style fixes 2022-05-01 14:50:23 +03:00
Konstantin Pavlov
2d2041a663 Fixed usedw[] calculations in preview_fifo. Other minor fixes 2020-10-30 11:51:59 +03:00
Konstantin Pavlov
3474f7b505 Updated dynamic_delay to allow delays bit-wize, not just element-wize 2019-06-28 01:28:45 +03:00
Konstantin Pavlov
57de1109bc Selector width fixed in dynamic_delay.sv 2019-04-14 00:07:00 +03:00
Konstantin Pavlov
2713e374c1 Lots of minor edits 2019-02-23 00:20:06 +03:00
Konstantin Pavlov (fm)
ba53bc5486 Updated SystemVerilog variants of delay modules 2019-01-09 14:59:39 +03:00