FPGA/basic_verilog
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10 Commits

Author SHA1 Message Date
Konstantin Pavlov
89b8dc6a3f Fixed Vivado gitignore 2024-05-28 10:28:40 +03:00
Konstantin Pavlov
454f71e80e HLS template project and scripts update 2023-03-12 21:09:32 +03:00
Konstantin Pavlov
978bed92bc KCPSM dir gitignore 2022-12-14 14:00:14 +03:00
Konstantin Pavlov
553e74c437 Updated Vivado gitignore 2022-11-11 14:29:24 +03:00
Konstantin Pavlov
3d0bb13dda Updated Vivado gitignore 2022-07-29 13:50:45 +03:00
Konstantin Pavlov
5abae5370e Update Modelsim gitignore 2022-07-03 16:38:37 +03:00
Konstantin Pavlov
49fefc9bf0 Straight and simple realization of recursive scripts 2022-06-16 06:59:32 +03:00
Konstantin Pavlov
2388fd3d54 Removed obsolete files. Updated scripts 2022-06-01 17:53:44 +03:00
Konstantin Pavlov
68ec41121e Added gitignore and clen script for Gowin IDE projects 2022-05-16 18:58:36 +03:00
Konstantin Pavlov
39490aed15 Added typical .gitignore-files for FPGA projects 2021-10-28 10:03:57 +03:00