FPGA/basic_verilog
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2 Commits

Author SHA1 Message Date
Konstantin Pavlov
46e79a0d34 Added Wishbone interface 2023-10-29 13:57:06 +03:00
Konstantin Pavlov
4f10b2ad3d Add AXI interface definitions 2023-10-25 07:01:25 +03:00