FPGA/basic_verilog
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11 Commits

Author SHA1 Message Date
Konstantin Pavlov
66ff427e1e Added error suppression for Modelsim script 2022-04-25 01:03:37 +03:00
Konstantin Pavlov
fe28e261e6 Added clock jitter 2021-12-25 22:52:24 +03:00
Konstantin Pavlov
b87a6bfad0 Added testbench template 2021-11-01 14:47:08 +03:00
Konstantin Pavlov
ff356f13e0 Two random generators with different seed values 2020-02-28 17:55:54 +03:00
Konstantin Pavlov
431d06145b Added SIMULATION define to the testbench template 2019-05-24 14:23:19 +03:00
Konstantin Pavlov
2713e374c1 Lots of minor edits 2019-02-23 00:20:06 +03:00
Konstantin Pavlov (fm)
9c1670a472 Added sample asynchronous external device logic 2019-02-08 13:56:50 +03:00
Konstantin Pavlov (fm)
8e61fc2036 Added initialization for testbench clocks and resets 2019-01-29 13:24:06 +03:00
Konstantin Pavlov (fm)
6d933d2ea2 snake_case naming for clock divider and main testbench template 2018-12-11 15:42:09 +03:00
Konstantin Pavlov (fm)
6b22c900b1 Updated EdgeDetect module instantiation 2018-12-07 11:26:03 +03:00
Konstantin Pavlov
b7f3bee0fd Added SystemVerilog variant of main_tb 2018-08-01 07:02:29 +03:00