FPGA/basic_verilog
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5 Commits

Author SHA1 Message Date
Konstantin Pavlov
bb0897a409 Fix clog usage in pulse_stretch.sv 2023-05-23 11:50:21 +03:00
Konstantin Pavlov
2d2041a663 Fixed usedw[] calculations in preview_fifo. Other minor fixes 2020-10-30 11:51:59 +03:00
Konstantin Pavlov
ec0bdd4948 Minor fixes 2020-04-16 10:57:36 +03:00
Konstantin Pavlov
7c9acbfbf0 Added pulse_stretch.sv and testbench 2019-11-15 15:32:26 +03:00
Konstantin Pavlov
7dec15cfe5 Added pulse_stretch.sv module 2019-11-14 12:22:18 +03:00