FPGA/basic_verilog
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3 Commits

Author SHA1 Message Date
Konstantin Pavlov
257c7fdff7 Fix template typo, 'block' paramerer is default 2022-11-16 17:07:08 +03:00
Konstantin Pavlov
a6aa3c3893 Done fifo initialization 2022-04-25 01:06:34 +03:00
Konstantin Pavlov
db847e6e7e Added RAM templates 2022-03-31 20:20:15 +03:00