FPGA/basic_verilog
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3 Commits

Author SHA1 Message Date
Konstantin Pavlov
b1c07c9c5f Added Verilog versions of UART components 2022-07-12 20:03:13 +03:00
Konstantin Pavlov
f3075c28a2 Added SV version of UART receiver 2021-01-27 10:58:54 +03:00
Konstantin Pavlov
536a8b83d2 Rewriting UART modules to SystemVerilog 2021-01-26 15:30:56 +03:00