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Author SHA1 Message Date
Konstantin Pavlov
1a32f07dfc Added optional WIDTH parameter. Made reset signal to be asynchronous 2022-03-31 15:31:57 +03:00
Konstantin Pavlov
a928a6c326 Updated Vivado test project to v2. Digilent Arty board does supported now 2022-03-30 19:40:12 +03:00
Konstantin Pavlov
4c6c8eabb7 Minor fixes for Quartus test project 2022-03-30 19:28:46 +03:00
Konstantin Pavlov
a2f57048dc Added original DP RAM templates from Quartus and Vivado 2022-03-15 15:37:09 +03:00
Konstantin Pavlov
4563fe0f93 Added ascii hex file generator script 2022-02-20 08:13:37 +03:00
Konstantin Pavlov
c3362fb4a2 Added note on MIF file initialization 2022-02-20 06:39:03 +03:00
Konstantin Pavlov
343abf82f7 Added fifo initialization from file 2022-02-20 05:50:35 +03:00
Konstantin Pavlov
2fad2973d0 Added utility script 2022-02-20 05:17:05 +03:00
Konstantin Pavlov
a1608c2326 Added performance variant of encoder and tb 2021-12-25 22:56:16 +03:00
Konstantin Pavlov
76674549c3 Added teo types of encoders 2021-12-25 22:53:30 +03:00
Konstantin Pavlov
fe28e261e6 Added clock jitter 2021-12-25 22:52:24 +03:00
Konstantin Pavlov
090372196e Added AXI templates (originally from Vivado component wizard) 2021-12-24 16:37:13 +03:00
Konstantin Pavlov
36f89f2554 Rewritten arst conditions in cdc_strobe.sv 2021-12-15 11:17:10 +03:00
Konstantin Pavlov
b91f6adac5 Added batch update script for your git repos 2021-11-18 18:38:10 +03:00
Konstantin Pavlov
937edbeb98 Added recursive build script 2021-11-09 14:47:29 +03:00
Konstantin Pavlov
29df4d58b8 Quartus demands to split if conditions 2021-11-09 05:34:16 +03:00
Konstantin Pavlov
2499f3a2ea Added Intel HLS scripts and boilerplate 2021-11-03 17:45:33 +03:00
Konstantin Pavlov
6c5ef366e7 Added Vivado quick project template 2021-11-01 14:48:05 +03:00
Konstantin Pavlov
b87a6bfad0 Added testbench template 2021-11-01 14:47:08 +03:00
Konstantin Pavlov
a80efe16c1 Added more cleaning scripts 2021-10-28 11:46:38 +03:00
Konstantin Pavlov
39490aed15 Added typical .gitignore-files for FPGA projects 2021-10-28 10:03:57 +03:00
Konstantin Pavlov
9203d17a63 Added cleaning scripts 2021-10-28 10:02:41 +03:00
Konstantin Pavlov
fdede74311 Added scripts for back-annotate and git-merge 2021-10-18 09:23:55 +03:00
Konstantin Pavlov
bcc548f914 SImplified reverse_vector.sv code 2021-09-13 11:17:58 +03:00
Konstantin Pavlov
0e19b10433 Updated cdc_strobe. Used gray counter under the hood 2021-09-11 11:04:43 +03:00
Konstantin Pavlov
261e0565cf Added Vivado initialization code 2021-08-18 16:31:19 +03:00
Konstantin Pavlov
871c92454e Added exporting script for Vivado 2021-08-09 16:19:16 +03:00
Konstantin Pavlov
0cb8ee915c Updated version autoincrement script for Quartus 2021-07-29 13:19:29 +03:00
Konstantin Pavlov (ms)
5156db4ebc Added SMA and tb 2021-07-29 02:08:53 +03:00
Konstantin Pavlov (ms)
4cd95ad2dc Added universal block RAM fifo 2021-07-19 01:45:45 +03:00
Konstantin Pavlov
1efbd7c243 Added soft_latch module and testbench 2021-07-09 17:24:20 +03:00
Konstantin Pavlov
d262582ea9
Update README.md 2021-07-07 17:39:43 +03:00
Konstantin Pavlov
2845a2a836 Updated lifo module to support FWFT and normal modes 2021-07-06 14:15:35 +03:00
Konstantin Pavlov
452b3574ff Added single clock fifo modules (two variants) 2021-07-05 09:12:14 +03:00
Konstantin Pavlov
cb224284b1 Added synchronizer modules 2021-06-11 17:39:06 +03:00
Konstantin Pavlov
d8beb37f01 Added Vivado-specific scripts 2021-06-03 17:01:55 +03:00
Konstantin Pavlov
48e9ddef7e Added Modelsim cleaning script 2021-05-27 12:54:51 +03:00
Konstantin Pavlov
aa52420d17 Updated Quartus Makefile and the reference project 2021-04-12 12:45:55 +03:00
Konstantin Pavlov
111dbc65c6 Test project for iterative compilation Quartus projects 2021-02-05 16:13:27 +03:00
Konstantin Pavlov
3619810053 Added fast counter sources 2021-02-05 16:12:05 +03:00
Konstantin Pavlov
c243e1d918 Added Quartus Makefile. Customizable and gives faster compilation 2021-02-05 16:10:16 +03:00
Konstantin Pavlov
f3075c28a2 Added SV version of UART receiver 2021-01-27 10:58:54 +03:00
Konstantin Pavlov
536a8b83d2 Rewriting UART modules to SystemVerilog 2021-01-26 15:30:56 +03:00
Konstantin Pavlov
b4b191c26f Minor code style update 2021-01-26 15:24:09 +03:00
Konstantin Pavlov
cf3b4f5d20 Moved all bencmarks to the separate directory 2021-01-26 15:16:11 +03:00
Konstantin Pavlov
1b844726dc
Update README.md 2020-12-22 11:14:44 +03:00
Konstantin Pavlov
3760990e5a Added UART-like shifters for for simple synchronous messaging inside the FPGA or between FPGAs 2020-12-18 16:14:10 +03:00
Konstantin Pavlov
68922a34d2 Updated benchmark projects. Added 'benchmark_results.txt' that i got on my machine 2020-12-17 18:42:52 +03:00
Konstantin Pavlov
d44ef08c2c Added benchmark project for Xilinx ISE Design Suite 2020-12-17 17:58:16 +03:00
Konstantin Pavlov
fee423776f Updates clean script for Quartus projects 2020-12-15 17:19:48 +03:00