FPGA/basic_verilog
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4 Commits

Author SHA1 Message Date
Konstantin Pavlov
2713e374c1 Lots of minor edits 2019-02-23 00:20:06 +03:00
Konstantin Pavlov (fm)
6d933d2ea2 snake_case naming for clock divider and main testbench template 2018-12-11 15:42:09 +03:00
Konstantin Pavlov (fm)
6b22c900b1 Updated EdgeDetect module instantiation 2018-12-07 11:26:03 +03:00
Konstantin Pavlov (fm)
24312652ab Combinational implementation of EdgeDetector with zero latency 2018-12-04 12:33:26 +03:00