FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity
233 Commits 1 Branch 0 Tags
Commit Graph

4 Commits

Author SHA1 Message Date
Konstantin Pavlov
db847e6e7e Added RAM templates 2022-03-31 20:20:15 +03:00
Konstantin Pavlov
1a32f07dfc Added optional WIDTH parameter. Made reset signal to be asynchronous 2022-03-31 15:31:57 +03:00
Konstantin Pavlov
bb246b3568 Updated edge_detect to v.3 2020-05-22 15:59:50 +03:00
Konstantin Pavlov (fm)
6ec509c3c6 snake_case naming for edge detector 2018-12-11 15:34:14 +03:00