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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

244 Commits

Author SHA1 Message Date
Konstantin Pavlov
276aea1e87 Add packed array slicers 2023-10-18 08:39:40 +03:00
Konstantin Pavlov
64e0408e0c Added dsp_everywhere 2023-10-08 12:07:57 +03:00
Konstantin Pavlov
5020e0b13e Add combinational repeater module 2023-09-26 05:51:19 +03:00
Konstantin Pavlov
39c1b4cf02 Restored simplified Verilog version of edge_detect 2023-09-12 18:37:39 +03:00
Konstantin Pavlov
213e17c657 Add simple UDP Ethernet packet generator 2023-05-23 13:07:08 +03:00
Konstantin Pavlov
bb0897a409 Fix clog usage in pulse_stretch.sv 2023-05-23 11:50:21 +03:00
Konstantin Pavlov
f0edcd3af0 Update formatting 2023-05-23 11:30:21 +03:00
Konstantin Pavlov
0475ea0398 Fix typo 2023-05-23 11:12:22 +03:00
Konstantin Pavlov
b81fda635d Fixed out[] initialization 2023-05-22 13:53:54 +03:00
Konstantin Pavlov
71303a0823 Updated delayed_event testbench 2023-05-22 13:46:06 +03:00
Konstantin Pavlov
8043f65f2b Added info banner 2023-05-22 13:44:20 +03:00
Konstantin Pavlov
23709d8278 Generalized delayed_event code 2023-05-22 13:41:44 +03:00
Konstantin Pavlov
2e3551056b Updated debounce 2023-05-22 13:39:56 +03:00
Konstantin Pavlov
0a7385391a Added modelsim / questasim error code cat 2023-05-17 13:07:48 +03:00
Konstantin Pavlov
9d51a2b2d2 Upd clogb2 info 2023-04-25 15:24:36 +03:00
Konstantin Pavlov
93bb8db9b8 Added sample code 2023-03-29 13:07:39 +03:00
Konstantin Pavlov
319de86e86 Add scripts 2023-03-27 14:18:58 +03:00
Konstantin Pavlov
454f71e80e HLS template project and scripts update 2023-03-12 21:09:32 +03:00
Konstantin Pavlov
8b1b2ef6a3 Added ASCII-to-HEX 2023-03-12 20:51:10 +03:00
Konstantin Pavlov
eb72143194 README update 2023-03-12 20:50:32 +03:00
Konstantin Pavlov
3aa56798bd README update 2023-02-24 06:02:27 +03:00
Konstantin Pavlov
d046210740 Added Vitis HLS scripts and example 2023-02-24 06:01:53 +03:00
Konstantin Pavlov
baea1069cb Updated Gray functions 2023-02-24 05:59:40 +03:00
Konstantin Pavlov
0523320552 CP script update 2023-02-19 01:48:43 +03:00
Konstantin Pavlov
58c10b0fcb Added hex2ascii as a standalone module 2023-02-19 01:47:14 +03:00
Konstantin Pavlov
45a1621a4a Restored simplified Verilog version of delay.sv 2023-02-19 01:45:44 +03:00
Konstantin Pavlov
db681a4efe Pattern is being detected in any bit position now 2023-02-06 02:10:12 +03:00
Konstantin Pavlov
fd3835448a Added prog script 2022-12-29 17:16:39 +03:00
Konstantin Pavlov
11ca69c348 Fixed Questa support in testbench_template 2022-12-29 17:01:18 +03:00
Konstantin Pavlov
88db449245 Added updater script 2022-12-14 15:01:42 +03:00
Konstantin Pavlov
978bed92bc KCPSM dir gitignore 2022-12-14 14:00:14 +03:00
Konstantin Pavlov
06c2498504 Added xilinx board store 2022-12-14 13:59:33 +03:00
Konstantin Pavlov
bdfd79b542 Updated scripts 2022-12-14 13:58:09 +03:00
Konstantin Pavlov
50300add8a Added clean scripts .. 2022-12-12 03:26:08 +03:00
Konstantin Pavlov
ff72cd4ff6 Added clean scripts 2022-12-12 03:23:58 +03:00
Konstantin Pavlov
de068b7426 Removed obsolete files 2022-12-12 03:19:02 +03:00
Konstantin Pavlov
c06a419792 Updated test prj up to Vivado 2021.2 2022-12-12 03:10:17 +03:00
Konstantin Pavlov
72cb6ac1d2 More submodules 2022-12-09 16:02:14 +03:00
Konstantin Pavlov
b93545503e Added fresh submodule 2022-12-02 17:32:23 +03:00
Konstantin Pavlov
f894f0997d Add more stats 2022-11-16 17:42:14 +03:00
Konstantin Pavlov
257c7fdff7 Fix template typo, 'block' paramerer is default 2022-11-16 17:07:08 +03:00
Konstantin Pavlov
65e4657650 Minor fix for read_ahead_buf 2022-11-11 15:51:08 +03:00
Konstantin Pavlov
a9f7d50998 Added new benchmarks 2022-11-11 14:49:31 +03:00
Konstantin Pavlov
553e74c437 Updated Vivado gitignore 2022-11-11 14:29:24 +03:00
Konstantin Pavlov
f9cfe3935b Added XPM sources 2022-11-10 11:07:17 +03:00
Konstantin Pavlov
da92eddd80 Added swap script 2022-11-10 10:28:22 +03:00
Konstantin Pavlov
2543bcd567 Added scripts 2022-08-24 12:42:56 +03:00
Konstantin Pavlov
3d0bb13dda Updated Vivado gitignore 2022-07-29 13:50:45 +03:00
Konstantin Pavlov
b1c07c9c5f Added Verilog versions of UART components 2022-07-12 20:03:13 +03:00
Konstantin Pavlov
0d9f67ff80 Updated testbench template 2022-07-03 16:39:54 +03:00