FPGA/basic_verilog
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14 Commits

Author SHA1 Message Date
Konstantin Pavlov
699c489592 Added bin2pos and pos2bin combinational modules 2018-09-16 15:41:21 +03:00
Konstantin Pavlov
ca43500c00 Added ReverseVector combinational module 2018-09-16 01:20:23 +03:00
Konstantin Pavlov
2282e26c1f Added single-clock FIFO and LIFO buffer modules 2018-07-29 08:27:30 +03:00
Konstantin Pavlov (pt)
7bda757047 Added integer division module 2016-12-14 12:51:46 +03:00
Konstantin Pavlov (pt)
a045839afd Added extreme minimal UART implementations. Testing in progress 2016-04-07 13:42:47 +03:00
Konstantin Pavlov (pt)
ee9d1b9e66 Added UART receiver and transmitter modules 2016-03-30 21:33:41 +03:00
Konstantin Pavlov (pt)
c31bb14628 ActionBurst module and minor fixes 2016-03-23 21:18:08 +03:00
Konstantin Pavlov (en)
e5aed02305 Added StaticDelay. Updated Main_tb 2016-01-15 19:25:06 +03:00
Konstantin Pavlov (pt)
d3f999e07e Explicit nrst naming for better Quartus compatibility 2016-01-07 14:05:06 +03:00
Konstantin Pavlov (pt)
78403cdec0 Added instantiation templates and testbenches for selected modules 2016-01-01 22:39:14 +03:00
Konstantin Pavlov (pt)
c1b04ecd87 Fixed error in Synch module 2015-12-25 23:20:33 +03:00
Konstantin Pavlov (pt)
df4a0b222c Added testbench template 2015-12-18 00:28:22 +03:00
Konstantin Pavlov (pt)
40533743d7 Added altera cookbook 2015-12-15 22:44:58 +03:00
Konstantin Pavlov (pt)
25b74793e0 Initial commit 2015-12-14 21:13:15 +03:00