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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00

2 Commits

Author SHA1 Message Date
Konstantin Pavlov (fm)
cb280f51cf Fixed RS triggers declaration syntax 2019-01-09 15:12:55 +03:00
Konstantin Pavlov (fm)
842496f0da Updated SystemVerilog variants of SR trigger featuring dominant logic state 2019-01-09 14:28:29 +03:00