FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
Code Issues Releases Wiki Activity
259 Commits 1 Branch 0 Tags
Commit Graph

4 Commits

Author SHA1 Message Date
Konstantin Pavlov
36f89f2554 Rewritten arst conditions in cdc_strobe.sv 2021-12-15 11:17:10 +03:00
Konstantin Pavlov
29df4d58b8 Quartus demands to split if conditions 2021-11-09 05:34:16 +03:00
Konstantin Pavlov
0e19b10433 Updated cdc_strobe. Used gray counter under the hood 2021-09-11 11:04:43 +03:00
Konstantin Pavlov
cb224284b1 Added synchronizer modules 2021-06-11 17:39:06 +03:00