FPGA/basic_verilog
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3 Commits

Author SHA1 Message Date
Konstantin Pavlov
f74126e5d6 Minor style fixes 2022-05-01 14:50:23 +03:00
Konstantin Pavlov
2713e374c1 Lots of minor edits 2019-02-23 00:20:06 +03:00
Konstantin Pavlov (fm)
a6280adfde Added SystemVerilog version of clock divider 2019-01-09 14:38:52 +03:00