FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity
193 Commits 1 Branch 0 Tags
Commit Graph

4 Commits

Author SHA1 Message Date
Konstantin Pavlov
65c465506b Updated tb template with clock gen module 2022-06-19 20:18:37 +03:00
Konstantin Pavlov
783c33e268 Updated testbench template project 2022-06-16 06:57:56 +03:00
Konstantin Pavlov
66ff427e1e Added error suppression for Modelsim script 2022-04-25 01:03:37 +03:00
Konstantin Pavlov
b87a6bfad0 Added testbench template 2021-11-01 14:47:08 +03:00