FPGA/basic_verilog
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3 Commits

Author SHA1 Message Date
Konstantin Pavlov (pt)
f871b7c369 Returned back some condition checks in UartTxExtreme 2016-05-20 15:57:31 +03:00
Konstantin Pavlov (pt)
392bc24c8e UartExtreme rewrite and simulation done 2016-04-10 16:13:09 +03:00
Konstantin Pavlov (pt)
a045839afd Added extreme minimal UART implementations. Testing in progress 2016-04-07 13:42:47 +03:00