FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity
56 Commits 1 Branch 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Konstantin Pavlov
2713e374c1 Lots of minor edits 2019-02-23 00:20:06 +03:00
Konstantin Pavlov (fm)
2d8e67db35 snake_case for reverse_vector module and its testbench 2019-01-09 14:32:02 +03:00