FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity
30 Commits 1 Branch 0 Tags
Commit Graph

3 Commits

Author SHA1 Message Date
Konstantin Pavlov (fm)
6b22c900b1 Updated EdgeDetect module instantiation 2018-12-07 11:26:03 +03:00
Konstantin Pavlov (pt)
d3f999e07e Explicit nrst naming for better Quartus compatibility 2016-01-07 14:05:06 +03:00
Konstantin Pavlov (pt)
78403cdec0 Added instantiation templates and testbenches for selected modules 2016-01-01 22:39:14 +03:00