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Author SHA1 Message Date
Konstantin Pavlov
7399deb17d Added Avalon master templates 2019-05-24 14:03:34 +03:00
Konstantin Pavlov
5bde0a502e Added version generating script to example project 2019-04-16 04:46:38 +03:00
Konstantin Pavlov
cd16cc5f9c Auto-incrementing project version for Quartus IDE 2019-04-16 04:45:23 +03:00
Konstantin Pavlov
51951d842d Added classic TAN timing analizer report parsing 2019-04-16 04:44:25 +03:00
Konstantin Pavlov
6bdafa6d56 Added errors supression script for Vivado to allow 'proto' projects w/o pin assignments 2019-04-16 04:42:39 +03:00
Konstantin Pavlov
1fdc31ad05 Added quartus benchmarking project 2019-04-15 02:37:45 +03:00
Konstantin Pavlov
8c420a1570 Updated reporting script to write total ompilation time 2019-04-15 02:24:31 +03:00
Konstantin Pavlov
57de1109bc Selector width fixed in dynamic_delay.sv 2019-04-14 00:07:00 +03:00
Konstantin Pavlov
b6028753ef Minor tcl script fixes 2019-03-30 18:16:28 +03:00
Konstantin Pavlov
80bcda370b Added a bunch of TCL scripts 2019-03-30 18:01:20 +03:00
Konstantin Pavlov
bea7cad324 Added quick shortcut for Modelsim compilation 2019-03-11 00:10:07 +03:00
Konstantin Pavlov
fe43d58156 Drastically simplyfied universal SPI master 2019-03-11 00:08:56 +03:00
Konstantin Pavlov
fbb6ecff17 Added System Console initialization script 2019-03-10 21:05:01 +03:00
Konstantin Pavlov
732a6883d5 Added scripts directory. Added SOF to RBF converter 2019-03-10 20:35:09 +03:00
Konstantin Pavlov
0b8a793478 Fixed delay length 2019-02-27 15:08:26 +03:00
Konstantin Pavlov
2713e374c1 Lots of minor edits 2019-02-23 00:20:06 +03:00
Konstantin Pavlov
f04430c7a8 Added universal spi master module 2019-02-22 23:33:58 +03:00
Konstantin Pavlov (fm)
f8794b5c48 Added Modelsim compile TCL script 2019-02-11 11:39:06 +03:00
Konstantin Pavlov (fm)
9c1670a472 Added sample asynchronous external device logic 2019-02-08 13:56:50 +03:00
Konstantin Pavlov (fm)
8e61fc2036 Added initialization for testbench clocks and resets 2019-01-29 13:24:06 +03:00
Konstantin Pavlov (fm)
cb280f51cf Fixed RS triggers declaration syntax 2019-01-09 15:12:55 +03:00
Konstantin Pavlov (fm)
ba53bc5486 Updated SystemVerilog variants of delay modules 2019-01-09 14:59:39 +03:00
Konstantin Pavlov (fm)
a6280adfde Added SystemVerilog version of clock divider 2019-01-09 14:38:52 +03:00
Konstantin Pavlov (fm)
d971d108cf Removed obsolete delay modules 2019-01-09 14:34:45 +03:00
Konstantin Pavlov (fm)
a66013eb1c Removed obsolete RS trigger modules 2019-01-09 14:33:13 +03:00
Konstantin Pavlov (fm)
2d8e67db35 snake_case for reverse_vector module and its testbench 2019-01-09 14:32:02 +03:00
Konstantin Pavlov (fm)
842496f0da Updated SystemVerilog variants of SR trigger featuring dominant logic state 2019-01-09 14:28:29 +03:00
Konstantin Pavlov (fm)
d39ccb2dd7 Added paramater to instantiation template of delay.sv 2019-01-09 14:23:45 +03:00
Konstantin Pavlov (fm)
807cc4303d Added .ena input to delay.sv 2019-01-09 13:58:20 +03:00
Konstantin Pavlov (fm)
6d933d2ea2 snake_case naming for clock divider and main testbench template 2018-12-11 15:42:09 +03:00
Konstantin Pavlov (fm)
6ec509c3c6 snake_case naming for edge detector 2018-12-11 15:34:14 +03:00
Konstantin Pavlov (fm)
6b22c900b1 Updated EdgeDetect module instantiation 2018-12-07 11:26:03 +03:00
Konstantin Pavlov (fm)
24312652ab Combinational implementation of EdgeDetector with zero latency 2018-12-04 12:33:26 +03:00
Konstantin Pavlov
5e8c4c2ced Minor fixes and comments 2018-09-16 17:26:39 +03:00
Konstantin Pavlov
699c489592 Added bin2pos and pos2bin combinational modules 2018-09-16 15:41:21 +03:00
Konstantin Pavlov
ca43500c00 Added ReverseVector combinational module 2018-09-16 01:20:23 +03:00
Konstantin Pavlov
b7f3bee0fd Added SystemVerilog variant of main_tb 2018-08-01 07:02:29 +03:00
Konstantin Pavlov
f838698dda Removed tabs 2018-08-01 07:00:37 +03:00
Konstantin Pavlov
829d84b4c7 Added element counter initialization 2018-08-01 06:39:08 +03:00
Konstantin Pavlov
2282e26c1f Added single-clock FIFO and LIFO buffer modules 2018-07-29 08:27:30 +03:00
Konstantin Pavlov
fc47ffdcb7 Added SystemVerilog variants of clock divider and edge detector 2018-07-29 08:14:23 +03:00
Konstantin Pavlov (pt)
7bda757047 Added integer division module 2016-12-14 12:51:46 +03:00
Konstantin Pavlov (pt)
e1701818a5 Added ActionBurst2. Minor fix to ActionBurst 2016-12-13 15:11:03 +03:00
Konstantin Pavlov (pt)
0000b487e1 Uniform instantiation templates. Synch() renamed to StaticDelay() 2016-12-12 11:41:56 +03:00
Konstantin Pavlov (pt)
f871b7c369 Returned back some condition checks in UartTxExtreme 2016-05-20 15:57:31 +03:00
Konstantin Pavlov (pt)
392bc24c8e UartExtreme rewrite and simulation done 2016-04-10 16:13:09 +03:00
Konstantin Pavlov (pt)
a045839afd Added extreme minimal UART implementations. Testing in progress 2016-04-07 13:42:47 +03:00
Konstantin Pavlov (pt)
1de6441c14 Minor fixes 2016-04-01 03:34:05 +03:00
Konstantin Pavlov (pt)
ee9d1b9e66 Added UART receiver and transmitter modules 2016-03-30 21:33:41 +03:00
Konstantin Pavlov (pt)
9e19abc733 Added Xilinx Picoblaze and its Altera version Pacoblaze as a great HDL programming examples 2016-03-24 21:10:37 +03:00