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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00

15 Commits

Author SHA1 Message Date
Konstantin Pavlov
6b99e1fdab Added script to program Altera/Intel devices 2019-10-02 13:40:27 +03:00
Konstantin Pavlov
928bced8b1 Added iverilog-gtlwave simulation script for Windows 2019-09-30 01:33:19 +03:00
Konstantin Pavlov
7f1454e6f7 Updated TCL scripts 2019-07-28 12:26:13 +03:00
Konstantin Pavlov
066fd2f5dc Added Vivado post-flow script boilerplate 2019-06-28 03:18:13 +03:00
Konstantin Pavlov
5a05b4df56 Added helper script to launch and initialize system console 2019-05-24 14:16:41 +03:00
Konstantin Pavlov
6e6b4905c5 Renaming scripts 2019-05-24 14:14:43 +03:00
Konstantin Pavlov
cd16cc5f9c Auto-incrementing project version for Quartus IDE 2019-04-16 04:45:23 +03:00
Konstantin Pavlov
51951d842d Added classic TAN timing analizer report parsing 2019-04-16 04:44:25 +03:00
Konstantin Pavlov
6bdafa6d56 Added errors supression script for Vivado to allow 'proto' projects w/o pin assignments 2019-04-16 04:42:39 +03:00
Konstantin Pavlov
8c420a1570 Updated reporting script to write total ompilation time 2019-04-15 02:24:31 +03:00
Konstantin Pavlov
b6028753ef Minor tcl script fixes 2019-03-30 18:16:28 +03:00
Konstantin Pavlov
80bcda370b Added a bunch of TCL scripts 2019-03-30 18:01:20 +03:00
Konstantin Pavlov
bea7cad324 Added quick shortcut for Modelsim compilation 2019-03-11 00:10:07 +03:00
Konstantin Pavlov
fbb6ecff17 Added System Console initialization script 2019-03-10 21:05:01 +03:00
Konstantin Pavlov
732a6883d5 Added scripts directory. Added SOF to RBF converter 2019-03-10 20:35:09 +03:00