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mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00

79 Commits

Author SHA1 Message Date
Konstantin Pavlov (fm)
6b22c900b1 Updated EdgeDetect module instantiation 2018-12-07 11:26:03 +03:00
Konstantin Pavlov (fm)
24312652ab Combinational implementation of EdgeDetector with zero latency 2018-12-04 12:33:26 +03:00
Konstantin Pavlov
5e8c4c2ced Minor fixes and comments 2018-09-16 17:26:39 +03:00
Konstantin Pavlov
699c489592 Added bin2pos and pos2bin combinational modules 2018-09-16 15:41:21 +03:00
Konstantin Pavlov
ca43500c00 Added ReverseVector combinational module 2018-09-16 01:20:23 +03:00
Konstantin Pavlov
b7f3bee0fd Added SystemVerilog variant of main_tb 2018-08-01 07:02:29 +03:00
Konstantin Pavlov
f838698dda Removed tabs 2018-08-01 07:00:37 +03:00
Konstantin Pavlov
829d84b4c7 Added element counter initialization 2018-08-01 06:39:08 +03:00
Konstantin Pavlov
2282e26c1f Added single-clock FIFO and LIFO buffer modules 2018-07-29 08:27:30 +03:00
Konstantin Pavlov
fc47ffdcb7 Added SystemVerilog variants of clock divider and edge detector 2018-07-29 08:14:23 +03:00
Konstantin Pavlov (pt)
7bda757047 Added integer division module 2016-12-14 12:51:46 +03:00
Konstantin Pavlov (pt)
e1701818a5 Added ActionBurst2. Minor fix to ActionBurst 2016-12-13 15:11:03 +03:00
Konstantin Pavlov (pt)
0000b487e1 Uniform instantiation templates. Synch() renamed to StaticDelay() 2016-12-12 11:41:56 +03:00
Konstantin Pavlov (pt)
f871b7c369 Returned back some condition checks in UartTxExtreme 2016-05-20 15:57:31 +03:00
Konstantin Pavlov (pt)
392bc24c8e UartExtreme rewrite and simulation done 2016-04-10 16:13:09 +03:00
Konstantin Pavlov (pt)
a045839afd Added extreme minimal UART implementations. Testing in progress 2016-04-07 13:42:47 +03:00
Konstantin Pavlov (pt)
1de6441c14 Minor fixes 2016-04-01 03:34:05 +03:00
Konstantin Pavlov (pt)
ee9d1b9e66 Added UART receiver and transmitter modules 2016-03-30 21:33:41 +03:00
Konstantin Pavlov (pt)
9e19abc733 Added Xilinx Picoblaze and its Altera version Pacoblaze as a great HDL programming examples 2016-03-24 21:10:37 +03:00
Konstantin Pavlov (pt)
c31bb14628 ActionBurst module and minor fixes 2016-03-23 21:18:08 +03:00
Konstantin Pavlov (en)
2a3f609428 "Enable" input in DeBounce module 2016-01-19 19:23:27 +03:00
Konstantin Pavlov (en)
e5aed02305 Added StaticDelay. Updated Main_tb 2016-01-15 19:25:06 +03:00
Konstantin Pavlov (pt)
d3f999e07e Explicit nrst naming for better Quartus compatibility 2016-01-07 14:05:06 +03:00
Konstantin Pavlov (pt)
78403cdec0 Added instantiation templates and testbenches for selected modules 2016-01-01 22:39:14 +03:00
Konstantin Pavlov (pt)
c1b04ecd87 Fixed error in Synch module 2015-12-25 23:20:33 +03:00
Konstantin Pavlov (pt)
4a5b91219e Added pulse generator modules 2015-12-24 19:05:06 +03:00
Konstantin Pavlov (pt)
df4a0b222c Added testbench template 2015-12-18 00:28:22 +03:00
Konstantin Pavlov (pt)
40533743d7 Added altera cookbook 2015-12-15 22:44:58 +03:00
Konstantin Pavlov (pt)
25b74793e0 Initial commit 2015-12-14 21:13:15 +03:00