FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-14 06:42:54 +08:00
Code Issues Releases Wiki Activity
226 Commits 1 Branch 0 Tags
Commit Graph

10 Commits

Author SHA1 Message Date
Konstantin Pavlov
de068b7426 Removed obsolete files 2022-12-12 03:19:02 +03:00
Konstantin Pavlov
f894f0997d Add more stats 2022-11-16 17:42:14 +03:00
Konstantin Pavlov
a9f7d50998 Added new benchmarks 2022-11-11 14:49:31 +03:00
Konstantin Pavlov
e583c9f977 Added reference souce code dir 2022-05-16 19:44:36 +03:00
Konstantin Pavlov
864a6900b9 More README fixes 2022-05-16 19:39:38 +03:00
Konstantin Pavlov
8d569ce7a1 Fixed READMEs 2022-05-16 19:29:41 +03:00
Konstantin Pavlov
66733fa819 Added benchmark_projects dir README 2022-05-16 19:21:43 +03:00
Konstantin Pavlov
f6a5726184 Added reference benchmark project for Gowin IDE 2022-05-16 19:06:38 +03:00
Konstantin Pavlov
aa52420d17 Updated Quartus Makefile and the reference project 2021-04-12 12:45:55 +03:00
Konstantin Pavlov
cf3b4f5d20 Moved all bencmarks to the separate directory 2021-01-26 15:16:11 +03:00