FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-01-28 07:02:55 +08:00
Code Issues Releases Wiki Activity
226 Commits 1 Branch 0 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Konstantin Pavlov
f6a5726184 Added reference benchmark project for Gowin IDE 2022-05-16 19:06:38 +03:00
Konstantin Pavlov
cf3b4f5d20 Moved all bencmarks to the separate directory 2021-01-26 15:16:11 +03:00