FPGA/basic_verilog
1
0
Fork 0
mirror of https://github.com/pConst/basic_verilog.git synced 2025-02-04 07:12:56 +08:00
Code Issues Releases Wiki Activity
41 Commits 1 Branch 0 Tags
Commit Graph

4 Commits

Author SHA1 Message Date
Konstantin Pavlov (fm)
8e61fc2036 Added initialization for testbench clocks and resets 2019-01-29 13:24:06 +03:00
Konstantin Pavlov (fm)
6d933d2ea2 snake_case naming for clock divider and main testbench template 2018-12-11 15:42:09 +03:00
Konstantin Pavlov (fm)
6b22c900b1 Updated EdgeDetect module instantiation 2018-12-07 11:26:03 +03:00
Konstantin Pavlov
b7f3bee0fd Added SystemVerilog variant of main_tb 2018-08-01 07:02:29 +03:00